Publications Conferences

2024

A. Tyagi and S. Kvatinsky, "Assessing the Performance of Stateful Logic in 1-Selector 1-RRAM Crossbar Arrays", Proceedings of IEEE International Symposium on Circuits and Systems, May 2024. Paper for Assessing the Performance of Stateful Logic in 1-Selector 1-RRAM Crossbar Arrays
J. Li, Y. Cui, C. Wang, W. Liu, and S. Kvatinsky, "A Concealable RRAM Phtsically Unclonable Function Compatible with In-Memory Computing", Proceedings of the Design, Automation and Testing in Europe, March 2024. Paper for A Concealable RRAM Phtsically Unclonable Function Compatible with In-Memory Computing
N. Aflalo, E. Yalon, and S. Kvatinsky, "Bitwise Logic using Phase Change Memory Devices Based on the Pinatubo Architecture", Proceedings of the International Conference on VLSI Design, January 2024. Paper for Bitwise Logic using Phase Change Memory Devices Based on the Pinatubo Architecture
A. Gero, M. A. Hadish, and S. Kvatinsky, "Abstract Thinking of Beginning Electrical Engineering and Computer Science Students", International Conference on Interactive Collaborative Learning, Springer Nature, February 2024. Paper for Abstract Thinking of Beginning Electrical Engineering and Computer Science Students

2023

B. Perach, R. Ronen, and S. Kvatinsky, "Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory", IEEE International System-on-Chip Conference (SOCC), September 2023. Paper for Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory
B. Perach, R. Ronen, and S. Kvatinsky, "Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory", Proceedings of IEEE interregional NEWCAS Conference, June 2023 (in press). Paper for Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory
B. Perach, R. Ronen, and S. Kvatinsky, "On Consistency for Bulk-Bitwise Processing-in-Memory", Proceedings of IEEE/ACM International Symposium on High-Performance Computer Architecture, February 2023 (in press). Paper for On Consistency for Bulk-Bitwise Processing-in-Memory

2022

A. Gero, M. A. Hadish, and S. Kvatinsky, "Undergraduate Students’ Attitudes Toward an Engineering Course that Integrates Several Levels of Abstraction", Proceedings of the International Conference on Interactive Collaborative Learning and 51st International Conference on Engineering Pedagogy, pp. 491-497, September 2022. Paper for Undergraduate Students’ Attitudes Toward an Engineering Course that Integrates Several Levels of Abstraction
M.Zou, J.Zhou, X.Cui, W.Wang, and S.Kvatinsky, "Enhancing Security of Memristor Computing System Through Secure Weight Mapping", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2022 (in press). Paper for Enhancing Security of Memristor Computing System Through Secure Weight Mapping
B. Hoffer and S. Kvatinsky, "Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM", Proceedings of the IEEE International Conference on Nanotechnology (NANO), July 2022 (in press). Paper for Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAMAbstract for Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM
B. Oved, O. Leitersdorf, R. Ronen, and S. Kvatinsky, "HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory", Proceedings of the International Conference on Modern Circuits and Systems Technologies, June 2022 (in press). Paper for HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-MemoryAbstract for HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory
O. Leitersdorf, R. Ronen, and S. Kvatinsky, "MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic", Proceedings of the International Symposium on Circuits and Systems, May 2022 (in press). Paper for MatPIM: Accelerating Matrix Operations with Memristive Stateful LogicAbstract for MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic

2021

O. Leitersdorf, B. Perach, R. Ronen, and S. Kvatinsky , "Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory", Proceedings of the Design Automation Conference, December 2021. Paper for Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory
M. Khalifa, R. Ben-Hur, R. Ronen, O. Leitersdorf, L. Yavits, and S. Kvatinsky, "FiltPIM: In-Memory Filter for DNA Sequencing", Proceedings of the IEEE International Conference on Electronics Circuits and Systems (ICECS), pp. 1-6, November 2021. Paper for FiltPIM: In-Memory Filter for DNA Sequencing
O. Leitersdorf, R. Ronen, and S. Kvatinsky, "Making Memristive Processing-in-Memory Reliable", 28th IEEE International Conference on Electronics, Circuits and Systems (ICECS), November 2021. Paper for Making Memristive Processing-in-Memory Reliable
S. Kvatinsky, "Making Real Memristive Processing-in-Memory Faster and Reliable", Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-3, October 2021. Paper for Making Real Memristive Processing-in-Memory Faster and Reliable

2020

D. Bhattacharjee, A. Chattopadhyay, S. Dutta, R. Ronen, and S. Kvatinsky, "CONTRA: Area-Constrained Technology Mapping Framework for Memristive Memory Processing Unit", Proceeding of the IEEE International Conference on Computer Aided Design, November 2020 (in press) Paper for CONTRA: Area-Constrained Technology Mapping Framework for Memristive Memory Processing Unit
N. Peled, R. Ben-Hur, R. Ronen and S. Kvatinsky, "X-MAGIC: Enhancing PIM with Input Overwriting Capabilities", Proceedings of the IFIP/IEEE VLSI-SoC, pp. 64-69, October 2020 (in press) Paper for X-MAGIC: Enhancing PIM with Input Overwriting Capabilities
A. Eliahu, R. Ben-Hur, R. Ronen and S. Kvatinsky, "abstractPIM: Bridging the Gap Between Processing-in-Memory Technology and Instruction Set Architecture", Proceedings of the IFIP/IEEE VLSI-SoC, pp. 28-33, October 2020 (in press) Paper for abstractPIM: Bridging the Gap Between Processing-in-Memory Technology and Instruction Set Architecture
L. Danial, K. Sharma, and S. Kvatinsky, "A Pipelined Memristive Neural Network Analog-to-Digital Converter", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), October 2020 (in press). Paper for A Pipelined Memristive Neural Network Analog-to-Digital Converter
Loai Danial and Shahar Kvatinsky, "Breaking the Conversion Wall in Mixed-Signal Systems Using Neuromorphic Data Converters", 24th IEEE European Conference on Circuits, Theory and Design, September 2020 Paper for Breaking the Conversion Wall in Mixed-Signal Systems Using Neuromorphic Data Converters
N. Wainstein, G. Ankonina, S. Kvatinsky, and E. Yalon, "Nanosecond Probing of Phase Transition Properties in Chalcogenides using Embedded Heater-Thermometer", Proceedings of the Materials Research Society Spring Meeting, April 2020
L. Danial, V. Gupta, E. Pikhay, Y. Roizin, and S. Kvatinsky, "Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing", Proceedings of the Design, Automation and Testing in Europe, March 2020 Paper for Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic ComputingVideo for Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing

2019

B. Hoffer, J. Louis and S. Kvatinsky, "Performing Memristor-Aided Logic (MAGIC) using STT-MRAM", ICECS 2019 Paper for Performing Memristor-Aided Logic (MAGIC) using STT-MRAM
L. Daniel, K. Sharma, S. Dwivedi, and S. Kvatinsky , "Logarithmic Neural Network Data Converters Using Memristors for Biomedical Applications", IEEE Biomedical Circuits and Systems (BioCAS), pp. 1-4, October 2019 Paper for Logarithmic Neural Network Data Converters Using Memristors for Biomedical Applications
J. Vieira, E. Giacomin, Y. Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, and P.-E. Gaillardon, "A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories", Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2019 (in press). Paper for A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories
S. Kvatinsky, "Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU)", Proceeding of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, July 2019 (in press). Paper for Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU)
M. Ottavi, V. Gupta, S. Khandelwal, S. Kvatinsky, J. Mathew, E. Martinelli, and A. Jabir, "The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors", Proceedings of IEEE International Symposium on On-Line Testing and Robust System Design, July 2019 (in press). Paper for The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors
N. Wainstein, T. Tsabari, Y. Goldin, E. Yalon and S. Kvatinsky, "A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 290-295, July 2019 Paper for A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable InductorsAbstract for A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors
L. Danial, S. Thomas, and S. Kvatinsky, "Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks", Proceedings of the International Symposium on Circuits and Architectures, pp. 1-5, May 2019 Paper for Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks
B. Perach and S. Kvatinsky, "STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ", Proceedings of the Design, Automation and Test in Europe, pp. 264-267, March 2019 Paper for STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ
R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky, "SIMPLE MAGIC: Synthesis and Mapping of Boolean Functions for Memristor Aided Logic (MAGIC)", Proceeding of the IEEE International Conference on Computer Aided Design, pp. 225-232, November 2017.
KLA-Tencor Excellent Conference Paper Award.
Paper for SIMPLE MAGIC: Synthesis and Mapping of Boolean Functions for Memristor Aided Logic (MAGIC)

2018

H. Abo-Hanna, L. Danial, S. Kvatinsky , and R. Daniel, "Memristors as Artificial Biochemical Reactions in Cytomorphic Systems", ICSEEI2018 Paper for Memristors as Artificial Biochemical Reactions in Cytomorphic Systems
L. Danial and S. Kvatinsky, "Real-Time Trainable Data Converters for General Purpose Applications", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, July 2018 (in press). Paper for Real-Time Trainable Data Converters for General Purpose Applications
G. C. Adam, R. Badulescu, S. Iordanescu, N. Wainstein, and S. Kvatinsky, "A TiO2 – Based Radio Frequency Resistive Switch", Proceedings of the International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, June 2018
A. Haj-Ali, R. Ben-Hur, N. Wald, and S. Kvatinsky, "Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC", Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS), June 2018 (in press). Paper for Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC
N. Talati, A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, P.E. Gaillardon, and S. Kvatinsky, "Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines", Proceedings of the Design, Automation, and Test in Europe (DATE), March 2018 (in press). Paper for Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines

2017

H. Abo Hanna, L. Danial, S. Kvatinsky, and R. Daniel, "Modeling Biochemical Reactions and Gene Networks with Memristors", Proceeding of the IEEE Symposium on Biological Circuits and Systems, October 2017 Paper for Modeling Biochemical Reactions and Gene Networks with Memristors
J. Reuben, R. Ben-Hur, N. Wald, N. Talati, A. Haj Ali, P. Emmanuel Gaillardon, and S. Kvatinsky, "Memristive Logic: A Framework for Evaluation and Comparison", Proceeding of the IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation, September 2017 (in press). Paper for Memristive Logic: A Framework for Evaluation and Comparison
N. Wainstein and S. Kvatinsky, "An RF Memristor Model and Memristive Single-Pole Double-Throw Switches", Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 (in press). Paper for An RF Memristor Model and Memristive Single-Pole Double-Throw Switches
N. Talati, Z. Wang, and S. Kvatinsky, "Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes", Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 (in press). Paper for Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes
L. Azriel and S. Kvatinsky, "Towards a Memristive Hardware Secure Hash Function (MemHash)", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017 (in press). Paper for Towards a Memristive Hardware Secure Hash Function (MemHash)
S. Kvatinsky, R. Ben-Hur, N. Talati, and N. Wald, "mMPU: Memristive Memory Processing Unit", International Conference on Memristive Materials, Devices & Systems, April 2017
S. Hamdioui, S. Kvatinsky, G. Cauwenberghs, L. Xie, K. Bertels, N. Wald, S. Joshi, H. M. Elsayed, and H. Corporaal, "Memristor For Computing: Myth or Reality?", Proceedings of the Design, Automation and Testing in Europe, pp. 722-731, March 2017 Paper for Memristor For Computing: Myth or Reality?

2016

N. Wald and S. Kvatinsky, "Design Methodology for Stateful Memristive Logic Gates", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016 (in press). Paper for Design Methodology for Stateful Memristive Logic Gates
R. Ben-Hur and S. Kvatinsky, "Memristive Memory Processing Unit (MPU) Controller for In-Memory Processing", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016 (in press). Paper for Memristive Memory Processing Unit (MPU) Controller for In-Memory Processing
H. Ha, A. Pedram, S. Richardson, S. Kvatinsky, and M. Horowitz, "Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access", Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 1-12, October 2016 Paper for Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access
A. Vasilyev, N. Bhagdikar, S. Richardson, A. Pedram, S. Kvatinsky, and M. Horowitz, "Evaluating Programmable Architectures for Image and Vision Applications", Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 1-13, October 2016 Paper for Evaluating Programmable Architectures for Image and Vision Applications
E. Amrany, A. Drory, and S. Kvatinsky, "Logic Design with Unipolar Memristors", Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), September 2016 (in press)
Selected for postconference book (top 10 papers).
Paper for Logic Design with Unipolar Memristors
R. Ben-Hur, N. Talati, and S. Kvatinsky, "Algorithmic Considerations in Memristive Memory Processing Units (MPU)", Proceedings of the International Cellular Nanoscale Networks and their Applications, August 2016 (in press) Paper for Algorithmic Considerations in Memristive Memory Processing Units (MPU)
R. Ben-Hur and S. Kvatinsky, "Memory Processing Unit for In-Memory Processing", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, July 2016 (in press) Paper for Memory Processing Unit for In-Memory Processing
Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Write Sneak-Path Constraints Avoiding Disturbs in Memristor Crossbar Arrays", Proceedings of the IEEE International Symposium on Information Theory, pp. 950-954, July 2016. Paper for Write Sneak-Path Constraints Avoiding Disturbs in Memristor Crossbar Arrays
E. Rosenthal, S. Greshnikov, D. Soudry, and S. Kvatinsky, "A Fully Analog Memristor-Based Multilayer Neural Network with Online Backpropagation Training", Proceeding of the IEEE International Conference on Circuits and Systems, pp. 1394-1397, May 2016 Paper for A Fully Analog Memristor-Based Multilayer Neural Network with Online Backpropagation Training
M. Ramadan, S. Kvatinsky, and R. Ginosar, "Memristor Modeling", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016
L. Danial and S. Kvatinsky, "Memristive Artificial Neural Networks Based Analog to Digital Converter (ADC)", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016
R. Ben-Hur and S. Kvatinsky, "Processing within a Memristive Memory", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016

2015

Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, X. Liu, J. Kang, Y. Nishi, and H.-S. P. Wong, "Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array", Proceedings of the 2015 International Memory Workshop, pp. 1-4, May 2015 Paper for Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array

2014

S. Kvatinsky, Y. H. Nacson, R. Patel, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristive Multistate Pipeline Register", Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-2, July 2014 Paper for Memristive Multistate Pipeline Register
Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "On the Channel Induced by Sneak-Path Errors in Memristor Arrays", Proceedings of the International Conference on Signal Processing and Communication, pp. 1-6, July 2014 Paper for On the Channel Induced by Sneak-Path Errors in Memristor Arrays
S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memory Intensive Computing", Proceeding of the Annual Non-Volatile Memories Workshop, March 2014 Paper for Memory Intensive Computing

2013

Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-Path Constraints in Memristor Crossbar Arrays", Proceedings of the IEEE International Symposium on Information Theory, pp. 156-160, July 2013 Paper for Sneak-Path Constraints in Memristor Crossbar Arrays
Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-Path Constraints in Memristor Crossbar Arrays", Proceeding of the Annual Non-Volatile Memories Workshop, March 2013 Paper for Sneak-Path Constraints in Memristor Crossbar Arrays

2012

S. Kvatinsky, K. Talisveyberg. D. Fliter, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Models of Memristors for SPICE Simulations", Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, November 2012 Paper for Models of Memristors for SPICE Simulations
S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, "MRL - Memristor Ratioed Logic", Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-6, August 2012 Paper for MRL - Memristor Ratioed LogicPresentation for MRL - Memristor Ratioed Logic

2011

S. Kvatinsky, E.G. Friedman, A. Kolodny, and U.C. Weiser, "Memristor-based IMPLY Logic Design Flow", Proceedings of the IEEE 29th International Conference on Computer Design, pp.142-147, October 2011 Paper for Memristor-based IMPLY Logic Design FlowPresentation for Memristor-based IMPLY Logic Design Flow

2010

S. Kvatinsky, E. G. Friedman , A. Kolodny, and L. Schächter, "Power Grid Analysis Based on a Macro Circuits Model", Proceedings of the IEEE 26th Convention of Electrical and Electronics Engineers in Israel, pp. 708-712, November 2010 Paper for Power Grid Analysis Based on a Macro Circuits ModelPresentation for Power Grid Analysis Based on a Macro Circuits Model