Publications Conferences

Publications:
Book ChaptersJournalsConferencesTechnical ReportsMagazinesPatentsSelected TalksAll Publications

2017

R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky, "Synthesis and Mapping of Boolean Functions for Memristor Aided Logic (MAGIC)", Proceeding of the IEEE International Conference on Circuits Aided Design, November 2017 Paper for Synthesis and Mapping of Boolean Functions for Memristor Aided Logic (MAGIC)
H. Abu Hanna, L. Danial, S. Kvatinsky, and R. Daniel, "Modeling Biochemical Reactions and Gene Networks with Memristors"Paper for Modeling Biochemical Reactions and Gene Networks with Memristors
John Reuben, Rotem Ben-Hur, Nimrod Wald, Nishil Talati, Ameer Haj Ali, Pierre-Emmanuel Gaillardon, and Shahar Kvatinsky, "Memristive Logic: A Framework for Evaluation and Comparison", Proceeding of the IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation, September 2017 Paper for Memristive Logic: A Framework for Evaluation and Comparison
N. Wainstein and S. Kvatinsky, "An RF Memristor Model and Memristive Single-Pole Double-Throw Switches (in press).", Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 Paper for An RF Memristor Model and Memristive Single-Pole Double-Throw Switches (in press).
N. Talati, Z. Wang, and S. Kvatinsky, "Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes (in press)", Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 Paper for Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes  (in press)
L. Azriel and S. Kvatinsky, "Towards a Memristive Hardware Secure Hash Function (MemHash) (in press)", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017 Paper for Towards a Memristive Hardware Secure Hash Function (MemHash) (in press)
S. Kvatinsky, R. Ben-Hur, N. Talati, and N. Wald, "mMPU: Memristive Memory Processing Unit", International Conference on Memristive Materials, Devices & Systems, April 2017
S. Hamdioui, S. Kvatinsky, G. Cauwenberghs, L. Xie, K. Bertels, N. Wald, S. Joshi, H. M. Elsayed, and H. Corporaal, "Memristor For Computing: Myth or Reality?", Proceedings of the Design, Automation and Testing in Europe, pp. 722-731, March 2017 Paper for Memristor For Computing: Myth or Reality?

2016

N. Wald and S. Kvatinsky, "Design Methodology for Stateful Memristive Logic Gates", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016 Paper for Design Methodology for Stateful Memristive Logic Gates
R. Ben-Hur and S. Kvatinsky, "Memristive Memory Processing Unit (MPU) Controller for In-Memory Processing", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016 Paper for Memristive Memory Processing Unit (MPU) Controller for In-Memory Processing
H. Ha, A. Pedram, S. Richardson, S. Kvatinsky, and M. Horowitz, "Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access", Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 1-12, October 2016 Paper for Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access
A. Vasilyev, N. Bhagdikar, S. Richardson, A. Pedram, S. Kvatinsky, and M. Horowitz, "Evaluating Programmable Architectures for Image and Vision Applications", Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 1-13, October 2016 Paper for Evaluating Programmable Architectures for Image and Vision Applications
E. Amrany, A. Drory, and S. Kvatinsky, "Logic Design with Unipolar Memristors", Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), September 2016 (in press) Paper for Logic Design with Unipolar Memristors
R. Ben-Hur, N. Talati, and S. Kvatinsky, "Algorithmic Considerations in Memristive Memory Processing Units (MPU)", Proceedings of the International Cellular Nanoscale Networks and their Applications, August 2016 (in press) Paper for Algorithmic Considerations in Memristive Memory Processing Units (MPU)
R. Ben-Hur and S. Kvatinsky, "Memory Processing Unit for In-Memory Processing", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, July 2016 (in press) Paper for Memory Processing Unit for In-Memory Processing
Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Write Sneak-Path Constraints Avoiding Disturbs in Memristor Crossbar Arrays", Proceedings of the IEEE International Symposium on Information Theory 2016 (in press) Paper for Write Sneak-Path Constraints Avoiding Disturbs in Memristor Crossbar Arrays
S. Greshnikov, E. Rosenthal, D. Soudry, and S. Kvatinsky, "A Fully Analog Memristor-Based Multilayer Neural Network with Online Backpropagation Training", Proceeding of the IEEE International Conference on Circuits and Systems, pp. 1394-1397, May 2016 Paper for A Fully Analog Memristor-Based Multilayer Neural Network with Online Backpropagation Training
M. Ramadan, S. Kvatinsky, and R. Ginosar, "Memristor Modeling", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016
L. Danial and S. Kvatinsky, "Memristive Artificial Neural Networks Based Analog to Digital Converter (ADC)", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016
R. Ben-Hur and S. Kvatinsky, "Processing within a Memristive Memory", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016

2015

Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, X. Liu, J. Kang, Y. Nishi, and H.-S. P. Wong, "Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array", Proceedings of the 2015 International Memory Workshop, pp. 1-4, May 2015 Paper for Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array

2014

S. Kvatinsky, Y. H. Nacson, R. Patel, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristive Multistate Pipeline Register", Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-2, July 2014 Paper for Memristive Multistate Pipeline Register
Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "On the Channel Induced by Sneak-Path Errors in Memristor Arrays", Proceedings of the International Conference on Signal Processing and Communication, pp. 1-6, July 2014 Paper for On the Channel Induced by Sneak-Path Errors in Memristor Arrays
S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memory Intensive Computing", Proceeding of the Annual Non-Volatile Memories Workshop, March 2014 Paper for Memory Intensive Computing

2013

Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-Path Constraints in Memristor Crossbar Arrays", Proceedings of the IEEE International Symposium on Information Theory, pp. 156-160, July 2013 Paper for Sneak-Path Constraints in Memristor Crossbar Arrays
Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Sneak-Path Constraints in Memristor Crossbar Arrays", Proceeding of the Annual Non-Volatile Memories Workshop, March 2013 Paper for Sneak-Path Constraints in Memristor Crossbar Arrays

2012

S. Kvatinsky, K. Talisveyberg. D. Fliter, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Models of Memristors for SPICE Simulations", Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, November 2012 Paper for Models of Memristors for SPICE Simulations
S. Kvatinsky, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, "MRL - Memristor Ratioed Logic", Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-6, August 2012 Paper for MRL - Memristor Ratioed LogicPresentation for MRL - Memristor Ratioed Logic

2011

S. Kvatinsky, E.G. Friedman, A. Kolodny, and U.C. Weiser, "Memristor-based IMPLY Logic Design Flow", Proceedings of the IEEE 29th International Conference on Computer Design, pp.142-147, October 2011 Paper for Memristor-based IMPLY Logic Design FlowPresentation for Memristor-based IMPLY Logic Design Flow

2010

S. Kvatinsky, E. G. Friedman , A. Kolodny, and L. Schächter, "Power Grid Analysis Based on a Macro Circuits Model", Proceedings of the IEEE 26th Convention of Electrical and Electronics Engineers in Israel, pp. 708-712, November 2010 Paper for Power Grid Analysis Based on a Macro Circuits ModelPresentation for Power Grid Analysis Based on a Macro Circuits Model