Resources Undergraduate Projects

Hardware SecurityRF, Mixed Signal and Analog CircuitsNeural NetworksComputer ArchitectureLogic with Memristors

Hardware Security

Design and Security Analysis of an AES Encryption Module
Abstract:

Side Channel Analysis is a group of attacks that utilize side effects of implementations of cryptographic hardware to gain access to secrets. One of such attacks is a Differential Power Analysis (DPA). DPA is an extremely powerful technique that uses power consumption as a source of leakage. For this, many power traces of execution of cryptographic algorithm are collected and processed. Machine learning techniques are then used to correlate between the power traces and the secret keys. It was first published in 1996, and since then hundreds of works have been published on successful DPA attacks of different types and on protection methods.

Description:
High Precision Differential Sense Amplifier for Resistive Memories
Abstract:

Background: Resistive memory is a new technology based on a passive circuit element called Memristor, which changes its resistance value based on the current flowing through it. Memristors are nanoscale elements that can be easily integrated in a typical VLSI manufacturing process. Therefore, memristors can be combined with existing structures to create new circuits. Memristors have a list of unique properties, such as non-volatility, non-linearity and sensitivity to process that make them particularly attractive for security applications. One such application is a memristive hardware secure hash function, based on a memristor crossbar structure. This application uses differential read and requires high accuracy in the read path. In this project, the students will design a high precision differential sense amplifier required for an accurate read from the array based on the state-of-the-art technology.
Project Description:
At the first stage, the students will study the literature related to high precision differential current sense amplifiers. Then, they will choose a specific architecture and design the circuit. In the following stage, the students will simulate the circuit both as a stand-alone and when connected to a memristor crossbar array. The simulations will include noise and parameter variations. The main tool for design and simulation is Cadence Virtuoso.

In this project the students will acquire experience in advanced analog design and in using the Cadence Analog Design Environment.

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RF, Mixed Signal and Analog Circuits

Memristor-Based Reconfigurable RF Amplifiers
Abstract:

The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the real challenge is scaling multi-frequency/multiprotocol RF systems and memristors can help us achieve that!

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Requirements:
Linear circuits, RFIC (recommended)
Memristor-Based Phase Shifters
Abstract:

The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the real challenge is scaling multi-frequency/multiprotocol RF systems and memristors can help us achieve that!

Description:
Supervisor(s):
Requirements:
Waves & Distributed systems, Circuit Theory, RFIC course (recommended)
Full Lab analysis of Σ-Δ Modulator as Memristor Driver
Abstract:

Memristors are considered a promising technology with very attractive properties, essentially two terminal thin‐film devices with non‐volatile varying analog resistance. It describes the relation between the flux and the electrical charge via integral on applied time interval. Therefore, it is equivalent to apply either a specific voltage for longer time or bigger voltage value for less time. This attribute makes the memristor a good candidate to work with encoded pulses completely compatible with sigma‐delta modulator.

Thanks to the memristor properties, artificial intelligence hardware is now achievable either for brain simulations or for building machine learning accelerator for running machine learning algorithms based on artificial neural networks. A major challenge in machine learning algorithms is to converge to global optimal solution, depend on the limited hardware precision and the number of layers. Therefore, in this project students are required to show that using sigma‐delta neurons will improve the precision and minimize the learning error dramatically.

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Neural Networks

Sigma-Delta Neuron for Memristor Learning
Abstract:

The artificial intelligent era has begun! From autonomous cognitive cars to brain-inspired neuromorphic integrated circuits that adaptively interact and precisely trained using the transmitted data. Huge efforts are invested to develop artificial neurons that mimic the functionality of neuro-processing and learning elements.

Biological neurons exchange information by transceiving spikes or pulse trains with other neurons. We show that sigma-delta modulators can be used to model the neural activation. A sigma-delta modulator is an efficient method for encoding analog signals into digital signals as found on high-precision analog to digital converters. While the memristor is used to model the synapse which represents the connection strength between neurons and the firing rate between them.

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Supervisor(s):
Requirements:
Linear electric circuits; recommended: Introduction to Biological Signals & Systems, Mixed-Signals Circuits

Computer Architecture

Automatic Loop-Unrolling Conversion to Multi-Threads Enabled of CEVA DSP Code
Abstract:

Modern computer systems contain a variety of mechanisms, designed to speed up the execution of certain types of programs. Two examples of such mechanisms are:

  • Loop unrolling, a software tweak that takes loops in a source code and unwinds them so that in each modified iteration, several iterations of the original code are performed. The unrolling itself is done either at compilation time or at runtime, and is somewhat dependent on the independence of statements from different iterations.
  • Multithreading: a hardware mechanism that allows multiple threads of code to run “simultaneously”. While the processor width is not changed, there can be no actual simultaneity between threads. But when one thread faces a delay in execution, another independent thread can continue its execution, thus increasing the total throughput.

Each of these may work better with different software, or even with different compilations of the same code. So a SW/HW vendor needs to choose which of the two (if any) to make optimizations for.

Description:
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Requirements:
234267 or 046267 – Computer Architecture, 236360 or 046266 – Compilation; recommended: 046267 – Computer Architecture, 044160 – EE Lab 1
MRAM versus SRAM for non volatile FIFO
Abstract:

Toggle MRAM uses a 1 transistor, 1 MTJ cell to provide a simple, high-density memory. Everspin uses a patented Toggle cell design that delivers high reliability. Data are always non-volatile for 20-years at temperature. During a read, the pass transistor is activated and data is read by comparing the resistance of the cell to a reference device. During writes, the magnetic field from Write Line 1 and Write Line 2 writes the cell at the intersection of the two lines but does not disturb other cells on either line. MRAM products employ one transistor, one magnetic tunnel junction (MTJ) memory cell for the storage element. The MTJ is composed of a fixed magnetic layer, a thin dielectric tunnel barrier and a free magnetic layer. When a bias is applied to the MTJ, electrons that are spin-polarized by the magnetic layers traverse the dielectric barrier through a process known as tunneling.

Project Description:
– Study the theory of Magnetic RAM and its interface
– Write an interface on FPGA to standard SRAM 35nsec
– Make a circuit including a MRAM and a SRAM
– Connect the circuit to the FPGA and debug the interface with SRAM
– Compare SRAM and MRAM performances
– Write a FIFO interface for the MRAM and demonstrate functionality
– Propose a MRAM application and develop it on the FPGA Board

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Supervisor(s):
New Non volatile Memory Technologies: FRAM Versus ReRAM
Abstract:

Nonvolatile memories that have traditionally been ROM (read only memory) until the advent of floating-gate technology. Floating-gate technology produced electrically erasable memories such as flash and EEPROM. These products allow for in-system programming but read and write access times are dissimilar. In fact, the write access times can be several orders of magnitude greater than the read access times. Ferroelectric random access memory or F-RAM is a true nonvolatile RAM because it combines the advantages of both RAM and nonvolatile memory. The write advantages over flash/EEPROM and non-volatility make it quite suitable for storing data in the absence of power.
Resistive random access memory. A form of non-volatile memory in which a pulse voltage is applied to a metal oxide thin film, creating massive changes in resistance to record ones and zeros. With a simple structure of metal oxide placed between electrodes, the manufacturing process is very simple, while still offering such excellent features as low power consumption and fast write.

Project Description: Study the theory of Ferroelectric RAM and Resistive RAM, Study the SPI and I²C interfaces, using available Libraries write an interface on FPGA to standard Serial RAM, design and make a circuit including a FRAM and a RRAM, connect the circuit to the FPGA and debug the interface, compare FRAM and RRAM performances by means of throughput and Magnetic Field Immunity, propose a FRAM and RRAM applications and demonstrate feasibility.

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RISC-V infrastructure bring-up
Abstract:

RISC-V is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education and is now set to become a standard open architecture for industry implementations. The RISC-V will become a part of the ASIC² lab tool box for project development in the field of Energy efficient computer architecture and more.
This challenging project includes a definition of RISC-V core, ISA and SOFTWARE, an implementation on Xilinx FPGA, coding of Basic Software, compilation and run on FPGA. Organize libraries for future Project at lab.

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Logic with Memristors

Design of Peripheral Circuit of Memory Array to Perform In-Memory Logic Operations
Abstract:

A memristive device (or a ‘memristor’ in short) is a two-terminal device whose resistance is determined by an internal state, which can be varied by the application of a voltage/current. The capability to toggle resistance (between a Low Resistance State – LRS, and a High Resistance State- HRS) in response to voltage/current is perhaps the most desirable property of memristors, extending their use from memory to computing. They are promising candidates for in-memory computing to solve the von-neumann bottleneck. MAGIC1(Memristor Aided logic) is a memristive logic family which can be used to implement in-memory computing. Combinational logic can be executed in the memory array efficiently using MAGIC logic family.

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Advanced Algorithms for Processing In Memory, Floating Point and Benchmarks
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In this project the students will investigate, research emerging technologies and computer architectures, and have a deep understanding of how inter-parallelism could be used to enhance the performance. Students will also have hands on the accelerator mMPU (memristive Memory Processing Unit), analyze its behavior, develop, map, simulate and evaluate different important and advanced benchmarks (e.g., floating point, deep learning, count, data/compute intensive applications, etc.). In addition, students will implement the logic functionality in memristor based transpose memory based on MAGIC NOR operations, optimize its performance, energy consumption, and area and compare it to the state-of-the-art implementation.
The project requires enthusiastic, excellent, and research oriented students capable of analyzing and deeply understand new ideas and technologies fast to derive unprecedented work which could replace the current state-of-the-art equivalents.

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Automatic Creation of In-Memory Controller
Abstract:

Background: Nowadays, the performance of computer systems is significantly limited by the speed of the memory. Data transportation between the memory and the processor is time consuming and wasteful in energy.
One of the leading ideas for solving these issues is to transfer part of the processing capabilities of the processor into the memory itself. For data-intensive applications, this means a significant increase in computing processing power, while saving a significant amount of time and energy.
A new computer architecture approach, based on a memristor-based memory, enables performing computations within the memory.
The memristor is a passive circuit element, predicted in 1971 by the circuit theorist Leon Chua. The first prototype of this element was unveiled in 2008 by HP labs. The device remembers its history,by varying its own resistance, so it can be used for memory applications. It also enables the formation of basic logic circuits, based on the MAGIC logic gate. The combine of memory with logic enables to perform logic operations within the memory itself, thus to explore advanced non-von Neumann architectures.
In previous work, we developed a tool which outputs the execution sequence of any desired logic operation. Additionally we designed a VHDL controller for controlling the in-memory computation. Now a combination of the two is desired.

Project Description:
In this project, the students will generate a code (c, python,…) which automatically creates the state machine of a controller, according to execution sequence which is provided as input.

Description:
Supervisor(s):
Executing state machines within a memristor-based memory
Abstract:

Nowadays, the performance of computer systems is significantly limited by the speed of the memory. Data transportation between the memory
and the processor is time-consuming and wasteful in energy.

One of the leading ideas for solving these issues is to transfer part of the processing capabilities of the processor into the memory itself. For data-
intensive applications, this means a significant increase in computing processing power, while saving a significant amount of time and energy.

A new computer architecture approach, based on a memristor-based memory, enables performing computations within the memory.
The memristor is a passive circuit element, predicted in 1971 by the circuit theorist Leon Chua. The first prototype of this element was unveiled
in 2008 by HP labs. The device remembers its history, by varying its own resistance, so it can be used for memory applications. It also enables
the formation of basic logic circuits, based on the MAGIC logic gate. The combine of memory with logic enables to perform logic operations
within the memory itself, thus to explore advanced non-von Neumann architectures.
Project description:
In this project, the students will design and implement an algorithm for executing state machines within a memristor-based memory. Such a
novel method enables to implement a processor within the memory, thus eliminate the need for an external processor in small systems, and
therefore reduces the limitations of today’s computer systems.

Description:
Supervisor(s):
In-Memory Searching Vs. Conventional Architectures
Abstract:

Background: Nowadays, the performance of computer systems is significantly limited by the speed of the memory. Data transportation between the memory and the processor is time consuming and wasteful in energy.
Searching quickly is one of the most desired capability in the big data era. In conventional architectures, as the data size increase, the latency for searching increases, since more data has to be transferred from the memory which stores the data to the processor which performs the searching. One of the leading ideas for solving these issue is to transfer the search process into the memory itself.
A new computer architecture approach, based on a memristor-based memory, enables performing computations within the memory.
The memristor is a passive circuit element, predicted in 1971 by the circuit theorist Leon Chua. The first prototype of this element was unveiled in 2008 by HP labs. The device remembers its history,by varying its own resistance, so it can be used for memory applications. It also enables the formation of basic logic circuits, based on the MAGIC logic gate. The combine of memory with logic enables to perform logic operations within the memory itself, thus to explore advanced non-von Neumann architectures.
In previous work we developed an algorithm for searching within memory.

Project Description:
In this project, the students will explore state of the art architectures which perform searching within big chunks of data and compare with results of in-memory computations.

Description:
Supervisor(s):
RRAM Basic Element Characterization and MAGIC implementation
Abstract:

Resistive Random Access Memory (RRAM) is an emerging technology based on the Memristor. It has made significant progress in the past decade as a competitive candidate for the next generation of non-volatile memory (NVM). But not only. Beyond the NVM applications, RRAM may also be used in Memristive Memory Computing applications. In this case RAM cells should go through a characterization procedure.

Project Description:
The project consists of learning Memristor technology and the process of characterization.
Study Memristor Basic Theory and specific Device Under Test (DUT)
Practice and control SMU & PS measurement techniques using LAN.
Design and implementation of a Test for DUT characterization
Learn MAGIC theory for in-memory computing
Implement a MAGIC gate in DC and for low frequency.
Design a test plan for MAGIC gate reliability test and evaluation of Mean Time Between Failures (MTBF).

Description:
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Resources:
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