Team Current Members
I am working on the design of energy-efficient non-von Neumann architectures using emerging memory technologies. I approach the problem from multiple perspectives, including, system architecture and circuit design. I focus on a special kind of memory technology, called, RRAM (Resistive Random Access Memory). My current work is based on a memory system design with this memory technology, and in future, I plan to focus on novel ways to perform computation within this memory to mitigate the memory wall problem in today’s state-of-the-art general-purpose computing machines. In the past, I worked on executing logical functions using RRAM from circuit design perspective.
(1) P. Mane, N. Talati, A. Riswadkar, R. Raghu, and C. Ramesha. “Reconfiguration on nanocrossbar using material implication,” Sadhana – Academy Proceedings in Engineering Science (Springer Publications), vol. 42, no. 1, pp. 33-44, Jan. 2017.
(2) N. Talati, S. Gupta, P. Mane, and S. Kvatinsky. “Logic design within memristive memories using Memristor Aided loGIC (MAGIC),” IEEE Transactions on Nanotechnology, vol. 15, no. 4, pp. 635-650, July 2016.
(3) P. Mane, N. Talati, A. Riswadkar, R. Raghu, and C. Ramesha. “Stateful-NOR based reconfigurable architecture for logic implementation,” Microelectronics Journal (Elsevier Publications), vol. 46, no. 6, pp. 551 – 562, 2015.
Conference and Workshop Publications:
(1) N. Talati, Z. Wang, and S. Kvatinsky, “Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes,” Proceeding of the IEEE International Conference on Circuits and Systems (ISCAS), May 2017 (in press).
(2) S. Kvatinsky, R. Ben-Hur, N. Talati, and N. Wald, “mMPU: Memristive Memory Processing Unit,” International Conference on Memristive Materials, Devices & Systems (MEMRISYS), April 2017.
(3) R. Ben-Hur, N. Talati, and S. Kvatinsky, “Algorithmic Considerations in Memristive Memory Processing Units (MPU),” Proceedings of the International Cellular Nanoscale Networks and their Applications (CNNA), August 2016.
(4) P. Mane, N. Talati, A. Riswadkar, B. Jasani, and C. Ramesha. “Implementation of NOR logic based on material implication on CMOL FPGA architecture,” in 28th International Conference on VLSI Design (VLSID), 2015, pp. 523 – 528, Jan 2015.
(5) P. Mane, N. Talati, A. Riswadkar, R. Raghu and C.K. Ramesha. “Implicating logic functions with memristors,” 11th International Conference on SoC Design (ISOCC), 2014, pp. 232 – 233, Nov 2014.
(1) R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky, ” Latency Optimized Mapping of Logic Functions for Memristor Aided Logic (MAGIC),” CCIT Technical Report #908, December 2016.