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Photo of Nishil Talati
Nishil Talati
Graduate Student

Research Summary

My research deals with alleviating the von Neumann bottleneck, and I approach the problem from several research directions, which predominantly include circuit and computer architecture design. Specifically, I am working on designing a low-cost, high capacity, scalable, and high-performance persistent memory system that can reduce the amount of costly accesses to the storage even for big data applications. Furthermore, I am working on devising novel data transfer mechanisms to align operands for in-memory computation in case of lack of locality. I believe that such techniques are extremely important to minimize the cost of data transfer and preserve the expected benefits of ‘in-memory’ computation.
In addition to my leadership role in these projects, I am also collaborating with my colleagues on various research projects including synthesis of logical functions for processing-in-memory and deep learning accelerator design.
During my undergrad, I worked on circuits and algorithms design for in-memory computing using RRAM.


Conference Publications:

(1) N. Talati, A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, P. E. Gaillardon, and S. Kvatinsky, “Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines,” Design, Automation, and Test in Europe DATE 2018.

(2) R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky. “SIMPLE MAGIC: Synthesis and In-memory Mapping of Logic Execution for Memristor Aided loGIC,” International Conference on Computer Aided Design ICCAD 2017.

(3) J. Ruben, R. Ben Hur, N. Wald, N. Talati, A. Haj Ali, P.E. Gaillardon, and S. Kvatinsky. “Memristive Logic: A Framework for Evaluation and Comparison,” International Symposium on Power and Timing Modeling, Optimization, and Simulations PATMOS 2017.

(4) N. Talati, Z. Wang, and S. Kvatinsky, “Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes,” International Symposium on Circuits and Systems ISCAS 2017.

(5) R. Ben Hur, N. Talati, and S. Kvatinsky, “Algorithmic Considerations in Memristive Memory Processing Units (MPU),” Proceedings of the International Cellular Nanoscale Networks and their Applications, August 2016.

(6) P. Mane, N. Talati, A. Riswadkar, B. Jasani, and C. Ramesha, “Implementation of NOR logic based on material implication on CMOL FPGA architecture,” 28th International Conference on VLSI Design (VLSID), 2015, pp. 523 – 528, Jan 2015.

(7) P. Mane, N. Talati, A. Riswadkar, R. Raghu and C.K. Ramesha, “Implicating logic functions with memristors,” 11th International Conference on SoC Design (ISOCC), 2014, pp. 232 – 233, Nov 2014.


Journal Publications:

(1) N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, “Logic design within memristive memories using Memristor Aided loGIC (MAGIC),” IEEE Transactions on Nanotechnology, vol. 15, no. 4, pp. 635-650, July 2016.

(2) P. Mane, N. Talati, A. Riswadkar, R. Raghu, and C. Ramesha, “Reconfiguration on nanocrossbar using material implication,” Sadhana-Academy Proceedings in
Engineering Science, vol. 42, no. 1, pp. 3344, Jan. 2017.

(3)P. Mane, N. Talati, A. Riswadkar, R. Raghu, and C. Ramesha, “Stateful-NOR based reconfigurable architecture for logic implementation,” Microelectronics Journal, vol. 46, no. 6, pp. 551 – 562, June 2015.

Book Chapters:

(1) N. Talati, R. Ben Hur, N. Wald, A. Haj Ali, J. Reuben, and S. Kvatinsky, “mMPU – a Real Processing–in–Memory Architecture to Combat the von Neumann Bottleneck,” in Advanced Applications of Emerging NVM Devices, Springer Series in Advanced Microelectronics, 2017 (in press).

(2) J. Reuben, N. Talati, N. Wald, R. Ben Hur, A. Haj Ali, P.E. Gaillardon, and S. Kvatinsky, “A Taxonomy and Evaluation Framework for Memristive Logic,” in Handbook of Memristor Networks, Springer, 2017 (in press).

Workshop Publications:

(1) S. Kvatinsky, R. Ben Hur, N. Talati, and N. Wald, “mMPU: memristive Memory Processing Unit,” MEMRISYS 2017.

(2) R. Ben Hur, N. Talati, Nimrod Wald, and Shahar Kvatinsky, “Memory Processing Unit for In-Memory Processing,” The First International Workshop on In-Memory and In-Storage Computing with Emerging Technologies (In Conjunction with 25th International Conference on Parallel Computing and Compilation Techniques (PACT)), 2016.

Technical Reports:

(1) R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky, ” Latency Optimized Mapping of Logic Functions for Memristor Aided Logic (MAGIC),” CCIT Technical Report #908, December 2016.

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