The paper introduces a 1S1R model tailored to a VO2-based selector and TiN/TiOx/HfOx/Pt RRAM device. We present simulations of 1R and 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
