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Prof. Shahar Kvatinsky has presented at EPFL, Switzerland on September 2017

September 5th, 2017

Prof. Shahar Kvatinsky has presented on September 28 at EPFL Workshop on “Logic Synthesis and Emerging Technologies” about “Logic Synthesis and Automation for Memristive Memory Processing Unit”.

Abstract – Memristors are capable of both store and process data within the same cells. This capability is the fundamental principle in the design of a memristive Memory Processing Unit (mMPU). The mMPU consists of a memristive memory array and a controller that supports memory and processing operations. For processing, the controller produces a sequence of basic logical operations that can be performed within the memristive memory array. In this talk, SIMPLE, a framework that optimizes the execution of an arbitrary logic function within a mMPU, while considering all the constraints involved in performing it within a memristive memory will be explained. SIMPLE automatically generates a defined sequence of atomic Memristive Aided Logic (MAGIC) NOR operations, whose implementation can be facilitated efficiently within the memory. Motivated to overcome the memory-CPU bottleneck, this approach designs an optimal solution in terms of performance by exploiting the parallelism of the MAGIC NOR gates. SIMPLE achieves performance speedups of 2X compared to a previous work and 1.5X compared to a naïve optimization based on standard synthesis tools.

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