J. Li, Y. Cui, C. Gu, C. Wang, W. Liu, and S. Kvatinsky,
"A Highly Reliable and Configurable RRAM PUF with a Key Concealment Scheme", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, January 2025.
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
N. Wainstein, A. Orren, R-G. Nir-Harwood, E. Yalon, and S. Kvatinsky,
"Asymmetric and Symmetric Single-Pole Double-Throw With Improved Power Handling Using Indirectly Heated Phase-Change Switches", IEEE Transactions on Electron Devices, January 2025.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, 2ϕ -JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel 2ϕ -JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These 2ϕ -JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
A. Mehonic, D. Ielmini, K. Roy, O. Mutlu, S. Kvatinsky, B. Linares-Barranco, S. Spiga, S. Savel'ev , A. G. Balanov, N. Chawla, G. Desol, G. Malavena, C. M. Compagnoni, Z. Wang, J. Yang, G. S. Syed, A. Sebastian, T. Mikolajick, B. Noheda, S. Slesazeck, B. Dieny, T.-H. Hou, A. Varri, F. Brückerhoff-Plückelmann, W. Pernice, X. Zhang, S. Pazos, M. Lanza, S. Wiefels, R. Ditmann, W. H. Ng, M. Buckwell, H. RJ Cox, D. J. Mannion, A. J. Kenyon, Y. Lu, Y. Yang, D. Querlioz, L. Hutin, E. Vianello, S. Shafayet Chowdhury, P. Mannocci, Y. Cai, Z. Sun, G. Pedretti, J. P. Strachan, D. Strukov, M. Le Gallo, S. Ambrogio, I. Valov, and R. Waser,
"Roadmap of Materials Challenges for Neuromorphic Computing", APL Materials, Vol. 12, No. 109201, October 2024.
The tunability of conductance states of various emerging nonvolatile memristive devices emulates the plasticity of biological synapses, making it promising in the hardware realization of large-scale neuromorphic systems. The inference of the neural network can be greatly accelerated by the vector-matrix multiplication (VMM) performed within a crossbar array of memristive devices in one step.
Nevertheless, the implementation of the VMM needs complex peripheral circuits, and the complexity further increases as non-idealities of memristive devices prevent precise conductance tuning (especially for the online training) and largely degrade the performance of the deep neural networks (DNNs). Herein, an efficient online training method of the memristive deep belief net (DBN) is presented. The proposed memristive DBN uses stochastically binarized activations, reducing the complexity of peripheral circuits, and uses the contrastive divergence (CD)-based gradient descent learning algorithm. The analog VMM and digital CD are performed separately in a mixed-signal hardware arrangement,
making the memristive DBN highly immune to non-idealities of synaptic devices.
The number of write operations on memristive devices is reduced by two orders of magnitude. The recognition accuracy of 95–97% can be achieved for the MNIST dataset using pulsed synaptic behaviors of various memristive synaptic devices.
M. Zou, Z. Zhu, T. Greenberg-Toledo, O. Leitersdorf, J. Li, J. Zhou, Y. Wang, N. Du, and S. Kvatinsky,
"TDPP: Two-Dimensional Permutation-Based Protection of Memristive Deep Neural Networks", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 43, No.3, pp. 742-755, March 2024.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
H. Padberg, A. Regev, G. Piccolboni, A. Bricalli, G. Molas, J. F. Nodin, and S. Kvatinsky,
"Experimental Demonstration of Non-Stateful In-Memory Logic with 1T1R SiOx Valence Change Mechanism Memristors", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 71, No. 1, pp. 395-399, January 2024.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
Z. Sun, S. Kvatinsky, X. Si, A. Mehonic, Y. Cai. and R. Huang ,
"A full spectrum of computing-in-memory technologies", Nature Electronics, November 2023.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
B. Perach, R. Ronen, B. Kimelfeld, and S. Kvatinsky,
"Understanding Bulk-Bitwise Processing In-Memory Through Database Analytics", IEEE Transactions on Emerging Topics in Computing, September 2023.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, 2ϕ -JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel 2ϕ -JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These 2ϕ -JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
O. Leitersdorf, Y. Boneh, G. Gazit, R. Ronen, and S. Kvatinsky,
"FourierPIM: High-throughput in-memory Fast Fourier Transform and polynomial multiplication", Memories - Materials, Devices, Circuits and Systems, Volume 4, July 2023.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
M. Khalifa, B. Hoffer, O. Leitersdorf, R. Hanhan, L. Yavits, and S. Kvatinsky,
"ClaPIM: Scalable Sequence CLAssification using Processing-In-Memory", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, July 2023 (in press).
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
O. Leitersdorf, D. Leitersdorf, J. Gal, M. Dahan, R. Ronen, and S. Kvatinsky,
"AritPIM: High-Throughput In-Memory Arithmetic", IEEE Transactions on Emerging Topics in Computing (TETC), April 2023.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
M. A. Hadish, S. Kvatinsky, and A. Gero,
"Learning and Instruction that Combine Multiple Levels of Abstraction in Engineering: Attitudes of Students and Faculty", International Journal of Engineering Education, Vol. 39, No. 1, pp. 154–162, 2023
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
W. Wang, L. Danial, Y. Li, E. Herbelin, E. Pikhay, Y. Roizin, B. Hoffer, Z. Wang, and S. Kvatinsky,
"A memristive deep belief neural network based on silicon synapses", Nature Electronics, December 2022.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
M. Zou, N. Du, and S. Kvatinsky,
"Review of Security Techniques for Memristor Computing Systems", Frontiers in Electronic Materials, December 2022.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
B. Hoffer, N. Wainstein, C. M. Neumann, E. Pop, E. Yalon, and S. Kvatinsky,
"Stateful Logic using Phase Change Memory", IEEE Journal of Exploratory Solid-State Computational Devices and Circuits Transactions on Electronic Devices, Vol. 8, No. 2, pp. 77-83, December 2022.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
Yang Li, Wei Wang, Di Zhang, Maria Baskin, Aiping Chen, Shahar Kvatinsky, Eilam Yalon, and Lior Kornblum,
"Scalable Al2O3-TiO2 Conductive Oxide Interfaces as Defect Reservoirs for Resistive Switching Devices", Advanced Electronic Material, November 2022.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
Z. Chen, G. Zhang, H. Cai, C. Bengel, F. Liu, X. Zhao, S. Kvatinsky, H. Schmidt, R. Waser, S. Menzel, and N. Du,
"Study on Sneak Path Effect in the Self-rectifying Crossbar Arrays based on Emerging Memristive Devices", Frontiers in Electronic Materials, October 2022, (in press).
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
I. Salameh, E. G. Friedman, and S. Kvatinsky,
"Superconducting Logic Using 2Φ Josephson Junctions with Half Flux Quantum Pulses", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, No. 5, pp. 2533-2537, May 2022.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, 2ϕ -JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel 2ϕ -JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These 2ϕ -JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
W. Wang, B. Hoffer, T. Greenberg-Toledo, Y. Li, E. Herbelin, R. Ronen, X. Xu, Y. Zhao, J. Yang, and S. Kvatinsky,
"Efficient Training of the Memristive Deep Belief Net Immune to Non-Idealities of the Synaptic Devices", Advanced Intelligent Systems, Vol. 4, No. 5, pp. 22100249, May 2022.
The tunability of conductance states of various emerging nonvolatile memristive devices emulates the plasticity of biological synapses, making it promising in the hardware realization of large-scale neuromorphic systems. The inference of the neural network can be greatly accelerated by the vector-matrix multiplication (VMM) performed within a crossbar array of memristive devices in one step.
Nevertheless, the implementation of the VMM needs complex peripheral circuits, and the complexity further increases as non-idealities of memristive devices prevent precise conductance tuning (especially for the online training) and largely degrade the performance of the deep neural networks (DNNs). Herein, an efficient online training method of the memristive deep belief net (DBN) is presented. The proposed memristive DBN uses stochastically binarized activations, reducing the complexity of peripheral circuits, and uses the contrastive divergence (CD)-based gradient descent learning algorithm. The analog VMM and digital CD are performed separately in a mixed-signal hardware arrangement,
making the memristive DBN highly immune to non-idealities of synaptic devices.
The number of write operations on memristive devices is reduced by two orders of magnitude. The recognition accuracy of 95–97% can be achieved for the MNIST dataset using pulsed synaptic behaviors of various memristive synaptic devices.
M. M. Dahan, E. T. Breyer, S. Slesazeck, T. Mikolajick, and S. Kvatinsky,
"C-AND: Mixed Writing Scheme for Disturb Reduction in 1T Ferroelectric FET Memory", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 69, No. 4, pp. 1595-1605, April 2022.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
W. Wang, L. Danial, E. Herbelin, B. Hoffer, B. Oved, T. Greenberg-Toledo, E. Pikhay, Y. Roizin, and S. Kvatinsky,
"Physical-Based Compact Model of Y-Flash Memristor for Neuromorphic Computation", Applied Physics Letters, Vol. 119, No. 26, December 2021.
The emerging memristive Memory Processing Unit (mMPU) overcomes the memory wall through memristive devices that unite storage and logic for real processing-in-memory (PIM)
systems. At the core of the mMPU is stateful logic, which is accelerated with memristive partitions to enable logic with massive inherent parallelism within crossbar arrays. This paper
vastly accelerates the fundamental operations of matrix-vector multiplication and convolution in the mMPU, with either fullprecision or binary elements. These proposed algorithms establish an efficient foundation for large-scale mMPU applications such as neural-networks, image processing, and numerical methods.
We overcome the inherent asymmetry limitation in the previous in-memory full-precision matrix-vector multiplication solutions by utilizing techniques from block matrix multiplication and reduction. We present the first fast in-memory binary matrixvector multiplication algorithm by utilizing memristive partitions with a tree-based popcount reduction (39× faster than previous work). For convolution, we present a novel in-memory inputparallel concept which we utilize for a full-precision algorithm that overcomes the asymmetry limitation in convolution, while also improving latency (2× faster than previous work), and the first fast binary algorithm (12× faster than previous work).
Y. Li, S. Kvatinsky, and L. Kornblum,
"Harnessing Conductive Oxide Interfaces for Resistive Random-Access Memories", Frontiers in Physics, (in press).
O. Leitersdorf, R. Ronen, and S. Kvatinsky,
"MultPIM: Fast Stateful Multiplication for Processing-in-Memory", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 69, No. 3, pp. 1647-1651, March 2022.
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
T. Greenberg-Toledo, B. Perach, I. Hubara, D. Soudry, S. Kvatinsky,
"Training of Quantized Deep Neural Networks using a Magnetic Tunnel Junction-Based Synapse", Semiconductor Science and Technology, Vol. 36, No. 11, October 2021.
M. Zou, J. Zhou, J. Sun, C. Ji, C. Wang, and S. Kvatinsky,
"Improving Efficiency and Lifetime of Logic-in-Memory by Combining IMPLY and MAGIC Families", Journal of Systems Architecture, Vol. 119, October 2021.
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
K. Stern, N. Wainstein, Y. Keller, C. M. Neumann, E. Pop, S. Kvatinsky, and E. Yalon,
"Sub-Nanosecond Pulses Enable Partial Reset for Analog Phase Change Memory", IEEE Electron Device Letters, Vol. 42, No. 9, pp. 1291-1294, September 2021.
R. Ronen, A. Eliahu, O. Leitersdorf, N. Peled, K. Korgaonkar, A. Chattopadhyay, B. Perach, and S. Kvatinsky,
"The Bitlet Model: A Parameterized Analytical Model to Compare PIM and CPU Systems", ACM Journal on Emerging Technologies in Computing Systems, Vol. 18, No. 2, Article No. 43, pp. 1-29, April 2022.
N. Wainstein, G. Ankonina, T. Swoboda, M. Muñoz Rojo, S. Kvatinsky, and E. Yalon,
"Indirectly Heated Switch as a Platform for Nanosecond Probing of Phase Transition Properties in Chalcogenides", IEEE Transactions on Electron Devices, Vol. 68, Issue 3, pp. 1298-1303, March 2021.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
D. Biolek, Z. Kolka, V. Biolkova, Z. Biolek, and S. Kvatinsky,
"(V)TEAM for SPICE Simulation of Memristive Devices with Improved Numerical Performance", IEEE Access, Vol. 9, No. 9, pp. 30242-30255, February 2021.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
N. Wainstein, E. Yalon, G. Adam, and S. Kvatinsky,
"Radiofrequency Switches Based on Emerging Resistive Memory Technologies - A Survey", Proceedings of the IEEE, Vol 109, No. 1, pp. 77-95, January 2021.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
N. Wainstein ,G. Ankonina, S. Kvatinsky, and E. Yalon,
"Compact Modeling and Electro-Thermal Measurements of Indirectly-Heated Phase Change RF Switches", IEEE Transactions on Electron Devices, Vol. 67, Issue 11, pp. 5182-5187, November 2020.
B. Hoffer, V. Rana, S. Menzel R. Waser, and S. Kvatinsky,
"Experimental Demonstration of Memristor-Aided Logic (MAGIC) Using Valence Change Memory (VCM)", IEEE Transactions on Electron Devices, Vol. 67, pp. 3115-3122, August 2020.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
D. Miron, D. Cohen Azarzar, B. Hoffer, M. Baskin, S. Kvatinsky, E. Yalon and L. Kornblum,
"Oxide 2D Electron Gases as a Reservoir of Defects for Resistive Switching", Applied Physics Letters, Vol.116, Issue 22, June 2020
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
H. Abo Hanna, L. Danial, S. Kvatinsky, and R. Daniel,
"Cytomorphic Electronics with Memristors for Modeling Fundamental Genetic Circuits", IEEE Transactions on Biomedical Circuits and Systems, Vol. 14, pp. 386-401, June 2020.
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
A. Eliahu, R. Ronen, P. E. Gaillardon, and S. Kvatinsky,
"multiPULPly: A Multiplication Engine for Accelerating Neural Networks on Ultra-Low-Power Architectures", ACM Journal on Emerging Technologies in Computing Systems, Vol. 1, No. 1, Article 1, January 2020.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
L. Danial, E. Pikhay, E. Herbelin, N. Wainstein, V. Gupta, N. Wald, Y. Roizin, R. Daniel, and S. Kvatinsky,
"Two-terminal floating-gate transistors with a low-power memristive operation mode for analogue neuromorphic computing", Nature Electronics, Vol. 2, pp. 596-605, December 2019.
Jacobs Best Paper Award
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
R. Ben-Hur, R. Ronen, A. Haj-Ali, D. Bhattacharjee, A. Eliahu, N. Peled, and S. Kvatinsky,
"SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 39, No. 10, pp. 2434-2447, October 2020.
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
B. Perach and S. Kvatinsky,
"An Asynchronous and Low-Power True Random Number Generator using STT-MTJ", IEEE Transactions on Very Large Scale Integration Systems, Vol. 27, No. 11, pp. 2473-2484, November 2019.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
M. Ramadan, N. Wainstein, R. Ginosar, S. Kvatinsky,
"Adaptive Programming in Multi-Level Cell ReRAM", Microelectronics Journal, Vol. 90, pp. 169-180, August 2019.
N. Wald and S. Kvatinsky,
"Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic", Microelectronics Journal, Vol. 86, pp. 22-33, April 2019
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
T. Greenberg, R. Mazor, A. Haj-Ali, and S. Kvatinsky,
"Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 4, pp. 1571-1583, April 2019.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
E. Giacomin, T. Greenberg, S. Kvatinsky, and P.-E. Gaillardon,
"A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No. 2, pp. 643-654, February 2019.
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
N. Talati, H. Ha, B. Perach, R. Ronen, and S. Kvatinsky,
"CONCEPT: A Column Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM", IEEE Micro, Vol. 39, No. 1, pp. 33-43, January/February 2019.
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
A. Haj-Ali, R. Ben-Hur, N. Wald, R. Ronen, and S. Kvatinsky,
"IMAGING-In-Memory AlGorithms for Image processiNG", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No 12, pp. 4258-4271, December 2018.
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
L. Danial, N. Wainstein, S. Kraus, and S. Kvatinsky,
"Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs using a Memristive Neuromorphic Architecture", IEEE Transactions on Emerging Topics in Computational Intelligence, Vol. 2, No.5, pp. 396-409, October 2018.
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, and S. Kvatinsky,
"Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing", IEEE Micro, Vol. 38, No. 5, pp. 13-21, September/October 2018.
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
N. Wainstein and S. Kvatinsky,
"A Lumped RF Model for Nanoscale Memristive Devices and Non-Volatile Single-Pole Double-Throw Switches", IEEE Transactions on Nanotechnology, vol. 17, no. 5, pp. 873-883, September 2018.
N. Wainstein and S. Kvatinsky,
"TIME – Tunable Inductors using MEmristors", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 5, pp. 1505-1515, May 2018.
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
L. Danial, N. Wainstein, S. Kraus, and S. Kvatinsky,
"DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 8, No. 1, pp. 146-158, March 2018.
The emerging memristive Memory Processing Unit (mMPU) overcomes the memory wall through memristive devices that unite storage and logic for real processing-in-memory (PIM)
systems. At the core of the mMPU is stateful logic, which is accelerated with memristive partitions to enable logic with massive inherent parallelism within crossbar arrays. This paper
vastly accelerates the fundamental operations of matrix-vector multiplication and convolution in the mMPU, with either fullprecision or binary elements. These proposed algorithms establish an efficient foundation for large-scale mMPU applications such as neural-networks, image processing, and numerical methods.
We overcome the inherent asymmetry limitation in the previous in-memory full-precision matrix-vector multiplication solutions by utilizing techniques from block matrix multiplication and reduction. We present the first fast in-memory binary matrixvector multiplication algorithm by utilizing memristive partitions with a tree-based popcount reduction (39× faster than previous work). For convolution, we present a novel in-memory inputparallel concept which we utilize for a full-precision algorithm that overcomes the asymmetry limitation in convolution, while also improving latency (2× faster than previous work), and the first fast binary algorithm (12× faster than previous work).
A. Doz, I. Goldstein, and S. Kvatinsky,
"Analysis of the Row Grounding Method in a Memristor-Based Crossbar Array", International Journal of Circuit Theory and Applications, Vol. 46, No. 1, pp. 122-137, January 2018
A. Pedram, S. Richardson, S. Galal, S. Kvatinsky and M. Horowitz,
"Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era", IEEE Design and Test, Vol. 34, No. 2, pp. 39-50, April 2017
Y. Cassuto, S. Kvatinsky, and E. Yaakobi,
"Information-Theoretic Sneak Path Mitigation in Memristor Crossbar Arrays", IEEE Transaction on Information Theory, Vol. 62, No. 9, pp. 4801-4814, September 2016.
N. Talati, S. Gupta, P. Mane, and S. Kvatinsky,
"Logic Design within Memristive Memories Using Memristor Aided loGIC (MAGIC)", IEEE Transactions on Nanotechnology, Vol. 15, No. 4, pp. 635-650, July 2016
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
A. Morad, L. Yavits, S. Kvatinsky, and R. Ginosar,
"Resistive GP-SIMD Processing In-Memory", ACM Transactions on Architecture and Code Optimization, Vol. 12, No. 4, Article 57, January 2016
L. Yavits, S. Kvatinsky, A. Morad, and R. Ginosar,
"Resistive Associative Processor", IEEE Computer Architecture Letters, Vol. 14, No. 2, July-December 2015
Best of CAL winner 2015
D. Soudry, D. Di Castro, A. Gal, A. Kolodny, and S. Kvatinsky,
"Memristor-based Multilayer Neural Networks with Online Gradient Descent Training", IEEE Transactions on Neural Networks and Learning Systems , Vol. 26, No. 10, pp. 2408-2421, October 2015
R. Patel, S. Kvatinsky, E. G. Friedman, and A. Kolodny,
"Multistate Register Based on Resistive RAM", IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 23, No. 9, pp. 1750-1759, September 2015
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny,
"VTEAM – A General Model for Voltage Controlled Memristor", Transactions on Circuits and Systems II: Express Briefs, Vol. 62, No. 8, pp. 786-790, August 2015
Y. Levy, J. Bruk, Y. Cassuto, E. G. Friedman, A. Kolodny, E. Yaacobi, and S. Kvatinsky,
"Logic Operation in Memory Using a Memristive Akers Array", Microelectronics Journal, Vol. 45, No. 11, pp. 1429-1437, November 2014
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"MAGIC – Memristor Aided LoGIC", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 11, pp. 895- 899, November 2014.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"Memristor-based Material Implication (IMPLY) Logic: Design Principles and Methodologies", IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 22, No. 10, pp. 2054-2066, October 2014
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"Memristor-based Multithreading", IEEE Computer Architecture Letters, Vol. 13, No. 1, pp. 41-44, January-June 2014
S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"The Desired Memristor for Circuit Designers", IEEE Circuits and Systems Magazine, second quarter, Vol. 13, No. 2, pp. 17-22, second quarter 2013
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"TEAM - ThrEshold Adaptive Memristor Model", IEEE Transactions on Circuits and Systems I: Regular Paper, Vol. 60, No. 1, pp. 211-221, January 2013
2015 Guillemin-Cauer Best Paper Award
O. Leitersdorf, R. Ronen, and S. Kvatinsky,
"PyPIM: Integrating Digital Processing-in-Memory from Microarchitectural Design to Python Tensors", Proceedings of IEEE/ACM International Symposium on Microarchitecture, November 2024.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, 2ϕ -JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel 2ϕ -JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These 2ϕ -JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
T. Patni, R. Daniels, and S. Kvatinsky,
"V-VTEAM: A Compact Behavioral Model for Volatile Memristors", IEEE International Flexible Electronics Technology Conference, September 2024.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, 2ϕ -JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel 2ϕ -JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These 2ϕ -JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
T. Neuner and S. Kvatinsky,
"Realization of Memristor Ratioed Logic with HfO2-Based Resistive RAM", IEEE International Conference on Electronics Circuits and Systems, November 2024.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
A. Tyagi and S. Kvatinsky,
"Assessing the Performance of Stateful Logic in 1-Selector 1-RRAM Crossbar Arrays", IEEE International Symposium on Circuits and Systems (ISCAS), May 2024.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
J. Li, Y. Cui, C. Wang, W. Liu, and S. Kvatinsky,
"A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing", Design, Automation and Testing in Europe, March 2024.
Superconductive logic based on Josephson junctions (JJ) is a promising technology for energy efficient supercomputers and cloud computing. This technology can deliver significant improvements in performance and energy efficiency as compared to CMOS. Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology, 2ϕ -JJ, has been proposed that eliminates the inductors. In this brief, three circuits are presented which exploit this scalable inductor-less technology. This novel 2ϕ -JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy. These 2ϕ -JJ logic circuits operate 2.25X faster and require 2.6X less energy as compared to RSFQ.
N. Aflalo, E. Yalon, and S. Kvatinsky,
"Bitwise Logic using Phase Change Memory Devices Based on the Pinatubo Architecture", International Conference on VLSI Design, January 2024.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
A. Gero, M. A. Hadish, and S. Kvatinsky,
"Abstract Thinking of Beginning Electrical Engineering and Computer Science Students", International Conference on Interactive Collaborative Learning, Springer Nature, February 2024.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
B. Perach, R. Ronen, and S. Kvatinsky,
"Enabling Relational Database Analytical Processing in Bulk-Bitwise Processing-In-Memory", IEEE International System-on-Chip Conference (SOCC), September 2023.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
B. Perach, R. Ronen, and S. Kvatinsky,
"Accelerating Relational Database Analytical Processing with Bulk-Bitwise Processing-in-Memory", Proceedings of IEEE interregional NEWCAS Conference, June 2023 (in press).
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
B. Perach, R. Ronen, and S. Kvatinsky,
"On Consistency for Bulk-Bitwise Processing-in-Memory", Proceedings of IEEE/ACM International Symposium on High-Performance Computer Architecture, February 2023 (in press).
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
A. Gero, M. A. Hadish, and S. Kvatinsky,
"Undergraduate Students’ Attitudes Toward an Engineering Course that Integrates Several Levels of Abstraction", Proceedings of the International Conference on Interactive Collaborative Learning and 51st International Conference on Engineering Pedagogy, pp. 491-497, September 2022.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
M.Zou, J.Zhou, X.Cui, W.Wang, and S.Kvatinsky,
"Enhancing Security of Memristor Computing System Through Secure Weight Mapping", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), July 2022 (in press).
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
B. Hoffer and S. Kvatinsky,
"Performing Stateful Logic Using Spin-Orbit Torque (SOT) MRAM", Proceedings of the IEEE International Conference on Nanotechnology (NANO), July 2022 (in press).
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
B. Oved, O. Leitersdorf, R. Ronen, and S. Kvatinsky,
"HashPIM: High-Throughput SHA-3 via Memristive Digital Processing-in-Memory", Proceedings of the International Conference on Modern Circuits and Systems Technologies, June 2022 (in press).
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
O. Leitersdorf, R. Ronen, and S. Kvatinsky,
"MatPIM: Accelerating Matrix Operations with Memristive Stateful Logic", Proceedings of the International Symposium on Circuits and Systems, May 2022 (in press).
The emerging memristive Memory Processing Unit (mMPU) overcomes the memory wall through memristive devices that unite storage and logic for real processing-in-memory (PIM)
systems. At the core of the mMPU is stateful logic, which is accelerated with memristive partitions to enable logic with massive inherent parallelism within crossbar arrays. This paper
vastly accelerates the fundamental operations of matrix-vector multiplication and convolution in the mMPU, with either fullprecision or binary elements. These proposed algorithms establish an efficient foundation for large-scale mMPU applications such as neural-networks, image processing, and numerical methods.
We overcome the inherent asymmetry limitation in the previous in-memory full-precision matrix-vector multiplication solutions by utilizing techniques from block matrix multiplication and reduction. We present the first fast in-memory binary matrixvector multiplication algorithm by utilizing memristive partitions with a tree-based popcount reduction (39× faster than previous work). For convolution, we present a novel in-memory inputparallel concept which we utilize for a full-precision algorithm that overcomes the asymmetry limitation in convolution, while also improving latency (2× faster than previous work), and the first fast binary algorithm (12× faster than previous work).
O. Leitersdorf, B. Perach, R. Ronen, and S. Kvatinsky ,
"Efficient Error-Correcting-Code Mechanism for High-Throughput Memristive Processing-in-Memory", Proceedings of the Design Automation Conference, December 2021.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
M. Khalifa, R. Ben-Hur, R. Ronen, O. Leitersdorf, L. Yavits, and S. Kvatinsky,
"FiltPIM: In-Memory Filter for DNA Sequencing", Proceedings of the IEEE International Conference on Electronics Circuits and Systems (ICECS), pp. 1-6, November 2021.
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
O. Leitersdorf, R. Ronen, and S. Kvatinsky,
"Making Memristive Processing-in-Memory Reliable", 28th IEEE International Conference on Electronics, Circuits and Systems (ICECS), November 2021.
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
S. Kvatinsky,
"Making Real Memristive Processing-in-Memory Faster and Reliable", Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-3, October 2021.
D. Bhattacharjee, A. Chattopadhyay, S. Dutta, R. Ronen, and S. Kvatinsky,
"CONTRA: Area-Constrained Technology Mapping Framework for Memristive Memory Processing Unit", Proceeding of the IEEE International Conference on Computer Aided Design, November 2020 (in press)
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
N. Peled, R. Ben-Hur, R. Ronen and S. Kvatinsky,
"X-MAGIC: Enhancing PIM with Input Overwriting Capabilities", Proceedings of the IFIP/IEEE VLSI-SoC, pp. 64-69, October 2020 (in press)
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
A. Eliahu, R. Ben-Hur, R. Ronen and S. Kvatinsky,
"abstractPIM: Bridging the Gap Between Processing-in-Memory Technology and Instruction Set Architecture", Proceedings of the IFIP/IEEE VLSI-SoC, pp. 28-33, October 2020 (in press)
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
L. Danial, K. Sharma, and S. Kvatinsky,
"A Pipelined Memristive Neural Network Analog-to-Digital Converter", Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), October 2020 (in press).
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
Loai Danial and Shahar Kvatinsky,
"Breaking the Conversion Wall in Mixed-Signal Systems Using Neuromorphic Data Converters", 24th IEEE European Conference on Circuits, Theory and Design, September 2020
The tunability of conductance states of various emerging nonvolatile memristive devices emulates the plasticity of biological synapses, making it promising in the hardware realization of large-scale neuromorphic systems. The inference of the neural network can be greatly accelerated by the vector-matrix multiplication (VMM) performed within a crossbar array of memristive devices in one step.
Nevertheless, the implementation of the VMM needs complex peripheral circuits, and the complexity further increases as non-idealities of memristive devices prevent precise conductance tuning (especially for the online training) and largely degrade the performance of the deep neural networks (DNNs). Herein, an efficient online training method of the memristive deep belief net (DBN) is presented. The proposed memristive DBN uses stochastically binarized activations, reducing the complexity of peripheral circuits, and uses the contrastive divergence (CD)-based gradient descent learning algorithm. The analog VMM and digital CD are performed separately in a mixed-signal hardware arrangement,
making the memristive DBN highly immune to non-idealities of synaptic devices.
The number of write operations on memristive devices is reduced by two orders of magnitude. The recognition accuracy of 95–97% can be achieved for the MNIST dataset using pulsed synaptic behaviors of various memristive synaptic devices.
N. Wainstein, G. Ankonina, S. Kvatinsky, and E. Yalon, "Nanosecond Probing of Phase Transition Properties in Chalcogenides using Embedded Heater-Thermometer", Proceedings of the Materials Research Society Spring Meeting, April 2020
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
L. Danial, V. Gupta, E. Pikhay, Y. Roizin, and S. Kvatinsky,
"Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic Computing", Proceedings of the Design, Automation and Testing in Europe, March 2020
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
B. Hoffer, J. Louis and S. Kvatinsky,
"Performing Memristor-Aided Logic (MAGIC) using STT-MRAM", ICECS 2019
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
L. Daniel, K. Sharma, S. Dwivedi, and S. Kvatinsky ,
"Logarithmic Neural Network Data Converters Using Memristors for Biomedical Applications", IEEE Biomedical Circuits and Systems (BioCAS), pp. 1-4, October 2019
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
J. Vieira, E. Giacomin, Y. Qureshi, M. Zapater, X. Tang, S. Kvatinsky, D. Atienza, and P.-E. Gaillardon,
"A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories", Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), October 2019 (in press).
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
S. Kvatinsky,
"Real Processing-in-Memory with Memristive Memory Processing Unit (mMPU)", Proceeding of the IEEE International Conference on Application-Specific Systems, Architectures and Processors, July 2019 (in press).
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
M. Ottavi, V. Gupta, S. Khandelwal, S. Kvatinsky, J. Mathew, E. Martinelli, and A. Jabir,
"The Missing Applications Found: Robust Design Techniques and Novel Uses of Memristors", Proceedings of IEEE International Symposium on On-Line Testing and Robust System Design, July 2019 (in press).
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
N. Wainstein, T. Tsabari, Y. Goldin, E. Yalon and S. Kvatinsky,
"A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable Inductors", Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), pp. 290-295, July 2019
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
L. Danial, S. Thomas, and S. Kvatinsky,
"Delta-Sigma Modulation Neurons for High-Precision Training of Memristive Synapses in Deep Neural Networks", Proceedings of the International Symposium on Circuits and Architectures, pp. 1-5, May 2019
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
B. Perach and S. Kvatinsky,
"STT-ANGIE: Asynchronous True Random Number GEnerator Using STT-MTJ", Proceedings of the Design, Automation and Test in Europe, pp. 264-267, March 2019
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
H. Abo-Hanna, L. Danial, S. Kvatinsky , and R. Daniel,
"Memristors as Artificial Biochemical Reactions in Cytomorphic Systems", ICSEEI2018
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
L. Danial and S. Kvatinsky,
"Real-Time Trainable Data Converters for General Purpose Applications", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, July 2018 (in press).
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
G. C. Adam, R. Badulescu, S. Iordanescu, N. Wainstein, and S. Kvatinsky, "A TiO2 – Based Radio Frequency Resistive Switch", Proceedings of the International Conference on Electron, Ion, and Photon Beam Technology and Nanofabrication, June 2018
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
A. Haj-Ali, R. Ben-Hur, N. Wald, and S. Kvatinsky,
"Efficient Algorithms for In-Memory Fixed Point Multiplication Using MAGIC", Proceeding of the IEEE International Symposium on Circuits and Systems (ISCAS), June 2018 (in press).
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
N. Talati, A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, P.E. Gaillardon, and S. Kvatinsky,
"Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines", Proceedings of the Design, Automation, and Test in Europe (DATE), March 2018 (in press).
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
R. Ben Hur, N. Wald, N. Talati, and S. Kvatinsky,
"SIMPLE MAGIC: Synthesis and Mapping of Boolean Functions for Memristor Aided Logic (MAGIC)", Proceeding of the IEEE International Conference on Computer Aided Design, pp. 225-232, November 2017.
KLA-Tencor Excellent Conference Paper Award.
Resistive Random Access Memory (RRAM) crossbar arrays are an attractive memory structure for emerging nonvolatile memory due to their high density and excellent scalability. Their ability to perform logic operations using RRAM devices makes them a critical component in non-von Neumann processing-in-memory architectures. Passive RRAM crossbar arrays (1-RRAM or 1R), however, suffer from a major issue of sneak path currents, leading to a lower readout margin and increasing write failures. To address this challenge, active RRAM arrays have been proposed, which incorporate a selector device in each memory cell (termed 1-selector-1-RRAM or 1S1R). The selector eliminates currents from unselected cells and therefore effectively mitigates the sneak path phenomenon. Yet, there is a need for a comprehensive analysis of 1S1R arrays, particularly concerning in-memory computation. In this paper, we introduce a 1S1R model tailored to a VO 2 -based selector and TiN/TiO x /HfO x /Pt RRAM device. We also present simulations of 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
H. Abo Hanna, L. Danial, S. Kvatinsky, and R. Daniel,
"Modeling Biochemical Reactions and Gene Networks with Memristors", Proceeding of the IEEE Symposium on Biological Circuits and Systems, October 2017
The growing demand for multi-band and multi-standard wireless devices requires flexible architectures that can reutilize the different blocks in the RF chains to reduce size and power consumption. The traditional multi-band radio with an RF chain per band is no longer scalable. Memristive devices have shown excellent performance as RF switches and also have a small footprint. Furthermore, as they are fabricated in the back-end of line of CMOS process, they enable tunability to integrated spiral inductors. In this paper, we present the design and simulations of a dual-band (2.4 GHz and 5 GHz) source degenerated low-noise amplifier (LNA) using memristive-via switched tunable inductors. Owing to the tunable inductor, the dual-band LNA has negligible area overhead compared to its single-band sibling. The LNA is designed using a 0.18-um RF CMOS technology and achieves a gain of 18.8 dB and 10.3 dB at 2.4 GHz and 5 GHz, respectively, and a noise figure (NF) below 2.3 dB at both bands. In addition, we present a semi-automated design methodology for the tunable inductors.
J. Reuben, R. Ben-Hur, N. Wald, N. Talati, A. Haj Ali, P. Emmanuel Gaillardon, and S. Kvatinsky,
"Memristive Logic: A Framework for Evaluation and Comparison", Proceeding of the IEEE International Symposium on Power and Timing Modeling, Optimization and Simulation, September 2017 (in press).
N. Wainstein and S. Kvatinsky,
"An RF Memristor Model and Memristive Single-Pole Double-Throw Switches", Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 (in press).
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
N. Talati, Z. Wang, and S. Kvatinsky,
"Rate-Compatible and High-Throughput Architecture Designs for Encoding LDPC Codes", Proceeding of the IEEE International Conference on Circuits and Systems, May 2017 (in press).
L. Azriel and S. Kvatinsky,
"Towards a Memristive Hardware Secure Hash Function (MemHash)", Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust (HOST), May 2017 (in press).
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
S. Kvatinsky, R. Ben-Hur, N. Talati, and N. Wald, "mMPU: Memristive Memory Processing Unit", International Conference on Memristive Materials, Devices & Systems, April 2017
Stateful logic is a promising processing-in-memory (PIM) paradigm to perform logic operations using emerging nonvolatile memory cells. While most stateful logic circuits to date focused on technologies such as resistive RAM, we propose two approaches to designing stateful logic using spinorbit torque (SOT) MRAM. The first approach utilizes the separation of read and write paths in SOT devices to perform logic operations. In contrast to previous work, our method utilizes a standard memory structure, and each row can be used as input or output. The second approach uses voltage-gated SOT switching to allow stateful logic in denser memory arrays.
We present array structures to support the two approaches and evaluate their functionality using SPICE simulations in the presence of process variation and device mismatch.
S. Hamdioui, S. Kvatinsky, G. Cauwenberghs, L. Xie, K. Bertels, N. Wald, S. Joshi, H. M. Elsayed, and H. Corporaal,
"Memristor For Computing: Myth or Reality?", Proceedings of the Design, Automation and Testing in Europe, pp. 722-731, March 2017
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
N. Wald and S. Kvatinsky,
"Design Methodology for Stateful Memristive Logic Gates", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016 (in press).
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
R. Ben-Hur and S. Kvatinsky,
"Memristive Memory Processing Unit (MPU) Controller for In-Memory Processing", Proceedings of the IEEE International Conference on Science of Electrical Engineering, November 2016 (in press).
H. Ha, A. Pedram, S. Richardson, S. Kvatinsky, and M. Horowitz,
"Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access", Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 1-12, October 2016
A. Vasilyev, N. Bhagdikar, S. Richardson, A. Pedram, S. Kvatinsky, and M. Horowitz,
"Evaluating Programmable Architectures for Image and Vision Applications", Proceedings of the Annual ACM/IEEE International Symposium on Microarchitecture, pp. 1-13, October 2016
E. Amrany, A. Drory, and S. Kvatinsky,
"Logic Design with Unipolar Memristors", Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), September 2016 (in press)
Selected for postconference book (top 10 papers).
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
R. Ben-Hur, N. Talati, and S. Kvatinsky,
"Algorithmic Considerations in Memristive Memory Processing Units (MPU)", Proceedings of the International Cellular Nanoscale Networks and their Applications, August 2016 (in press)
R. Ben-Hur and S. Kvatinsky,
"Memory Processing Unit for In-Memory Processing", Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, July 2016 (in press)
Y. Cassuto, S. Kvatinsky, and E. Yaakobi,
"Write Sneak-Path Constraints Avoiding Disturbs in Memristor Crossbar Arrays", Proceedings of the IEEE International Symposium on Information Theory, pp. 950-954, July 2016.
E. Rosenthal, S. Greshnikov, D. Soudry, and S. Kvatinsky,
"A Fully Analog Memristor-Based Multilayer Neural Network with Online Backpropagation Training", Proceeding of the IEEE International Conference on Circuits and Systems, pp. 1394-1397, May 2016
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
M. Ramadan, S. Kvatinsky, and R. Ginosar, "Memristor Modeling", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016
L. Danial and S. Kvatinsky, "Memristive Artificial Neural Networks Based Analog to Digital Converter (ADC)", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
R. Ben-Hur and S. Kvatinsky, "Processing within a Memristive Memory", Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016
Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, X. Liu, J. Kang, Y. Nishi, and H.-S. P. Wong,
"Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array", Proceedings of the 2015 International Memory Workshop, pp. 1-4, May 2015
S. Kvatinsky, Y. H. Nacson, R. Patel, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"Memristive Multistate Pipeline Register", Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-2, July 2014
Y. Cassuto, S. Kvatinsky, and E. Yaakobi,
"On the Channel Induced by Sneak-Path Errors in Memristor Arrays", Proceedings of the International Conference on Signal Processing and Communication, pp. 1-6, July 2014
S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"Memory Intensive Computing", Proceeding of the Annual Non-Volatile Memories Workshop, March 2014
Y. Cassuto, S. Kvatinsky, and E. Yaakobi,
"Sneak-Path Constraints in Memristor Crossbar Arrays", Proceedings of the IEEE International Symposium on Information Theory, pp. 156-160, July 2013
Y. Cassuto, S. Kvatinsky, and E. Yaakobi,
"Sneak-Path Constraints in Memristor Crossbar Arrays", Proceeding of the Annual Non-Volatile Memories Workshop, March 2013
S. Kvatinsky, K. Talisveyberg. D. Fliter, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"Models of Memristors for SPICE Simulations", Proceedings of the IEEE Convention of Electrical and Electronics Engineers in Israel, pp. 1-5, November 2012
S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser,
"MRL - Memristor Ratioed Logic", Proceedings of the International Cellular Nanoscale Networks and their Applications, pp. 1-6, August 2012
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
S. Kvatinsky, E.G. Friedman, A. Kolodny, and U.C. Weiser,
"Memristor-based IMPLY Logic Design Flow", Proceedings of the IEEE 29th International Conference on Computer Design, pp.142-147, October 2011
Recent research has sought to accelerate cryptographic hash functions as they are at the core of modern cryptography. Traditional designs, however, suffer from the von Neumann bottleneck that originates from the separation of processing and memory units. An emerging solution to overcome this bottleneck is processing-in-memory (PIM): performing logic
within the same devices responsible for memory to eliminate data-transfer and simultaneously provide massive computational parallelism. In this paper, we seek to vastly accelerate the stateof-the-art SHA-3 cryptographic function using the memristive memory processing unit (mMPU), a general-purpose memristive PIM architecture. To that end, we propose a novel in-memory algorithm for variable rotation, and utilize an efficient mapping of the SHA-3 state vector for memristive crossbar arrays to efficiently exploit PIM parallelism. We demonstrate a massive energy efficiency of 1, 422 Gbps/W, improving a state-of-the-art memristive SHA-3 accelerator (SHINE-2) by 4.6×.
S. Kvatinsky, E. G. Friedman , A. Kolodny, and L. Schächter,
"Power Grid Analysis Based on a Macro Circuits Model", Proceedings of the IEEE 26th Convention of Electrical and Electronics Engineers in Israel, pp. 708-712, November 2010
All Publications
