Memory Design & Methodologies
The scalability of DRAM is facing challenges owing to increased power consumption and difficulty to build high-aspect ratio capacitors. Commercially available flash memories suffer from low endurance, low yield, slower switching, etc. At ASIC2, we investigate emerging non-volatile memristive memory technologies, such as Resistive RAM (RRAM), Phase Change Memory (PCM), Spin-Transfer Torque Magnetoresistive RAM (STT-MRAM), Spin-Orbit Torque Magnetoresistive RAM (SOT-MRAM), Conductive Bridge RAM (CBRAM), as replacements for conventional memory technologies.
Memristive devices are fabricated between two metal layers, which act as top and bottom electrodes of the memristive dielectric material. Hence, dense memristive crossbar arrays can be fabricated in the metal layers, as part of the standard CMOS Back End Of Line (BEOL) process. At ASIC2, we attempt to solve the problems faced by current memory technologies by designing memristors for memory applications at various levels of memory hierarchy, for example, for main memory and storage class memory [1].
We develop compact models [2], [3] to explore memristive devices as memory and CAD tools to design memristive arrays for Random Access Memories (RAMs) and Content Addressable Memories (CAMs). Some of the peculiar properties of memristive memories include imbalanced write times for writing 1’s and 0’s, sneak path currents [4], write disturb phenomenon [5], etc. Our research group tries to solve these problems by appropriate circuit and architecture designs.
[1] Z. Jiang, P. Huang, L. Zhao, S. Kvatinsky, S. Yu, X. Liu, J. Kang, Y. Nishi, and H.-S. P. Wong, “Analysis and Predication on Resistive Random Access Memory (RRAM) 1S1R Array”, Proceedings of the 2015 International Memory Workshop, pp. 1-4, May 2015
[2] M. Ramadan, S. Kvatinsky, and R. Ginosar, “Memristor Modeling”, Proceedings of the Workshop on Memristor Technology, Design, Automation and Computing, January 2016
[3] S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, “VTEAM – A General Model for Voltage Controlled Memristors”, CCIT Technical Report #856, April 2014
[4] Y. Cassuto, S. Kvatinsky, and E. Yaakobi, “Sneak-Path Constraints in Memristor Crossbar Arrays”, Proceedings of the IEEE International Symposium on Information Theory, pp. 156-160, July 2013
[5] Y. Cassuto, S. Kvatinsky, and E. Yaakobi, “Write Sneak-Path Constraints Avoiding Disturbs in Memristor Crossbar Arrays”, Proceedings of the IEEE International Symposium on Information Theory, pp. 950-954, July 2016
