Research Memory Design & Methodologies

The scalability of DRAM is facing challenges owing to increased power consumption and difficulty to build high-aspect ratio capacitors. Commercially available flash memories suffer from low endurance, low yield, slower switching, etc. At ASIC2, we investigate emerging non-volatile memristive memory technologies, such as Resistive RAM (RRAM), Phase Change Memory (PCM), Spin-Transfer Torque Magnetoresistive RAM (STT-RAM), Conductive Bridge RAM (CBRAM) as replacements for conventional memory technologies.
Memristive devices are fabricated between two metal layers, which act as top and bottom electrodes of the memristive dielectric material. Hence, dense memristive crossbars can be fabricated in the metal layers, as part of the standard CMOS Back End Of Line (BEOL) process. At ASIC2, attempt to solve the problems faced by current memory technologies by designing memristors for memory applications at various levels of memory hierarchy, for example, for main memory and storage class memory.
Also, we engineer memristive memories for designing Content Addressable Memories (CAMs). Some of the peculiar properties of memristive memories include imbalanced write times for writing 1’s and 0’s, sneak path currents, write disturb phenomenon, etc. Our research group tries to solve these problems by appropriate circuit and architecture designs.

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