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Rotem Ben-Hur’s paper has been accepted to CATC 2018

October 2nd, 2018

Rotem Ben-Hur’s paper has been accepted to The Compiler, Architecture, and Tools Conference (CATC 2018)!

“Memristive Memory Processing Unit for Real In-Memory Processing”, Rotem Ben-Hur, Ronny Ronen, and Shahar Kvatinsky.

Abstract:

Data transfer between memory and CPU in a conventional von Neumann architecture is the
primary performance and energy bottleneck in modern computing systems. To reduce this
overhead, we are developing a new computer architecture that enables real in-memory
processing based on a unit that can both store and process data using the same cells. This unit,
called a memristive memory processing unit (mMPU), will substantially reduce the necessity of
moving data in computing systems. Emerging memory technologies, namely memristive
devices, are the enablers of the mMPU. While memristors are usually used as memory, these
novel devices can also perform logical operations using a technique we have invented called
Memristor Aided Logic (MAGIC). Different sequences of MAGIC NOR operations can be
used to execute any desired function within the memristive memory. Furthermore, the mMPU
naturally performs multiple parallel operations and therefore is an excellent SIMD (Single
Instruction Multiple Data) engine.
Although the mMPU has the potential to perform general purpose computations, the sequence
of MAGIC operations necessary to implement the desired function in-memory has to be
optimized in terms of performance, energy or area to be beneficial. For that purpose, we have
developed a flow and a memory optimizer tool that, first, automatically translate complex
function to MAGIC gates, and then, optimize their in-memory execution. By exploiting the
parallel processing capability offered by memristive memories and by reusing memory cells the
optimizer tool achieves significant performance speedup and area reduction.
In this talk, we will describe:
1. The mMPU architecture and its benefits – from the memristor cell, via the MAGIC gate,
to parallel execution of operation sequence.
2. The principles of the developed flow and memory optimizer tool.
3. Deeper look into the memory optimizer tool operation.

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