The exponential growth of data calls for increasing power efficiency in computation as well as scaling down the needed computation area. New emerging non-von Neumann technologies offer solutions to these challenges and are often based on memristive devices such as resistive RAM (ReRAM) and Yflash as building blocks. Resistive RAM (ReRAM) and Y-flash are great candidates for neuromorphic applications. The feasibility of the devices has to be evaluated by experimental characterization of the technologies using statistical measurements. By that, the variability (i.e. the variation of the measurement results between different cycles and different cells) can be determined, which is crucial for the accuracy of the application.
This project aims to statistically evaluate the variability of ReRAM by Weebit and Y-Flash devices fabricated in Tower 180 nm standard CMOS process. The devices will be measured and characterized to generate statistical information of device variability and reliability.
Emerging memristors are novel circuit elements, originally described as the “fourth missing circuit element” and considered today as the future of nonvolatile memory. Different memristors have been developed and simulatively characterized by the Technion’s ASIC² research group, headed by Prof. Shahar Kvatinsky. Current Compliance (CC) is a factor that can significantly influence the memristive devices performance.
State-of-the-art apparatus propose CC circuit with response time of 100𝜇Sec to 1mSec, this slow response time may cause undesired behavior of the memristive devices or even damage the device.
Our target is to potentially improve the measurement setup of research memristive devices by designing a small CC circuit.
Traditional approaches to storing secret keys in memory for cryptographic applications are susceptible to physical attacks when an attacker gains access to the storage medium. To address this issue, physically unclonable functions (PUFs) have emerged as a novel concept for secure key storage. PUFs store the cryptographic key as unique analog identifiers within the hardware, rather than in memory elements, making them resilient against physical attacks.
In this research, we propose the study of novel coating-based PUFs that leverage nanoscale inhomogeneity, randomness, and uniqueness in nanomaterials and nanostructures. Our study encompasses the design, simulations, fabrication, and characterization of physically unclonable coatings, along with the development of metrics to evaluate their effectiveness.
Emerging memristors are novel circuit elements, originally described as the “fourth missing circuit element” and considered today as the future of nonvolatile memory. Different memristors have been developed and simulatively characterized by the Technion’s ASIC² research group, headed by Prof. Shahar Kvatinsky.
Some of the memristor devices have been manufactured by semiconductor companies (such as Tower Semiconductor, Winbond, and Weebit) and some of them were fabricated in academia by our collaborators from universities such as Stanford, Aachen, and Arizona State.
Our target is to experimentally measure and characterize memristors and to demonstrate their functionality for novel circuits in applications such as artificial intelligence, memory, and logic.
Yflash is a memory device manufactured by Tower Semiconductor that consists of two transistors in series with a common drain and floating gate. This device can be used as an analogue memory element in its subthreshold region of operation and can have up to 65 stable conductance levels. When placed in a crossbar, this device can be used for various analogue brain-inspired computing applications like Hopfield networks, deep belief networks and artificial neural networks.
In this project, you will build a behavioural simulator of a Yflash crossbar array using MATLAB or python. This simulator must be able to model the behaviour of a real YFlash array. The crossbar must be scalable.
You will use this crossbar model for building a multilayer perceptron (MLP) type artificial neural network (ANN) and demonstrate its usage for handwritten digit recognition. You will then explore the scalability of YFlash arrays using larger datasets. You will also explore the scalability of the MLP ANN using multiple fixed size YFlash crossbars.
SNNs are the next generation neural networks with the ability to perform complex brain-like computations with very low power. SNNs use discrete ON/OFF signals called action potentials or spikes for data communication and processing.
In this project, you will simulate various building blocks of SNNs including the Hodgkin-Huxley Neuron, Leaky Integrate and Fire Neuron and its variants using memristors. You will also demonstrate concepts like Spike Time Dependent Plasticity (STDP), long term potentiation (LTP), long term depression (LTD) with memristive synapses.
You will also build feed forward spiking neural networks using these basic components. These circuits will be behaviourally implemented in MATLAB and then implemented in cadence virtuoso circuit simulator.
The exponential growth of data calls for increasing power efficiency in computation as well as scaling down the needed computation area. New emerging non-von Neumann technologies offer solutions to these challenges and are often based on memristive devices such as resistive RAM (ReRAM) and Yflash as building blocks. Resistive RAM (ReRAM) and Y-flash are great candidates for neuromorphic applications. The feasibility of the devices has to be evaluated by experimental characterization of the technologies. Many neuromorphic applications require multi-level devices with as many available levels as possible. Therefore, the experimental investigation aims for information about the number of levels and the accuracy of these levels.
This project aims for the experimental investigation of multi-level options of ReRAM by Weebit and Y-Flash devices fabricated in Tower 180 nm standard CMOS process. The devices will be measured and characterized to gain information about the multi-level properties.
