Computer architecture has a major bottleneck in the transfer of data between memory and computation units. One of the solutions that has been proposed is Compute-in-memory (CIM) architectures, to accelerate the computations. A key component in such mixed-signal CIM architectures is the Analog-to-Digital Converter (ADC), and in particular the Successive Approximation Register (SAR) ADC, which digitizes the analog computation results from RRAM crossbar arrays.
This project focuses on the circuit-level design and characterization of an 8-bit SAR ADC with a StrongARM comparator, inspired by the methodology presented in [1] [2]. The emphasis is on measuring and modeling the dynamic power consumption of the comparator and CDAC, as a function of input-dependent switching activity. The project includes characterization of energy per comparison, extracting CDAC switching energy as a function of output code and SAR decision step, and building a lookup table (LUT) for comparator dynamic energy versus differential input voltage. Through this work, students will experience mixed-signal circuit design, understand the role of ADCs in compute-in-memory architectures, and explore how analog design choices impact system-level behavior and potentially even security.
Scope of the project:
• Architecture design: Define the SAR ADC, with two main components
comparator and switched-capacitor DAC and timing requirements.
• Implementation and Verification: in Virtuoso, including layout.
SNNs are the next generation neural networks with the ability to perform complex brain-like computations with very low power. SNNs use discrete ON/OFF signals called action potentials or spikes for data communication and processing.
In this project, you will simulate various building blocks of SNNs including the Hodgkin-Huxley Neuron, Leaky Integrate and Fire Neuron and its variants using memristors. You will also demonstrate concepts like Spike Time Dependent Plasticity (STDP), long term potentiation (LTP), long term depression (LTD) with memristive synapses.
You will also build feed forward spiking neural networks using these basic components. These circuits will be behaviourally implemented in MATLAB and then implemented in cadence virtuoso circuit simulator.
Recently, several dif ferent NVM memory technologies (NAND Flash, PCM, ReRAM, STT-MRAM)
have emerged as promising candidates for digital and analog in-memory computation.
Tower Jazz’s Y-Flash Non-Volatile Memory can be used as a building block which can be used in
many ANN applications.
In this project you learn the FPGA environment and use it to build an emulator which functions as an
ideal Y-Flash cell and presents a multilevel output current.
Recently, several different nonvolatile memory (NVM) technologies, such as NAND Flash, PCM,
ReRAM, and STT-MRAM, have emerged as promising candidates for digital and analog in-memory
computation. Tower’s Y-Flash NVM, fully compatible with standard CMOS process, can be used as a
building block which can be used in many artificial neural networks (ANNs) applications owing its
multilevel characteristic.
In this project, you develop an experimental setup to write the weights of an ANN to a Y-Flash memory
array. This project is part of the NEMO project, where we aim to implement ultra-low-power ANN
hardware accelerators.
Traditional Transformers are computationally expensive due to dense matrix multiplications and Softmax operations. Recent research in neuromorphic computing has introduced Spike-driven Self-Attention (SDSA) [1], which replaces these multiplications with sparse additions, achieving x87.2 lower energy costs than the vanilla self-attention, making them ideal for hardware acceleration.
This project aims to design and implement an FPGA accelerator that exploits this sparsity to achieve energy-efficient inference.
Project Objectives
In this project, students will build a digital SNN architecture on an FPGA that specifically implements the building blocks of a Spiking Transformer.
Particularly, students will:
1. Implement spiking neuron models on FPGA: use fixed-point arithmetic to implement the snntorch* neuron models, ensuring they match the python training environment.
2. Implement spike-driven attention: design a digital module that uses the spiking neurons and performs “mask-and-add” operations instead of the standard dot-product attention.
3. Quantization & sparsity analysis: study the trade-offs between bit-width and accuracy.
4.Power & timing analysis (FPGA): estimate dynamic power using FPGA-specific tools (e.g., Vivado power analyzer).
a.Optimize pipeline latency to ensure the transformer can process temporal sequences in real-time.
*snntorch is a python library which makes training spiking neural network easier.
Spiking Neural Networks (SNNs) are a promising paradigm for energy-efficient artificial intelligence, mimicking the sparse and temporal nature of biological neural processing. To achieve ultra-low-power consumption, these networks can be implemented using analog hardware operating in the subthreshold regime, where transistors operate with currents in the [𝑝𝐴−𝑛𝐴] range. However, a significant challenge lies in the precise synchronization between custom physical hardware and the digital models used for training and validation.
Project Objectives
In this project, students will develop a unified framework for a biologically plausible spiking neuron by matching a custom analog implementation with a “Digital Twin” Python model.
Particularly, students will:
1. Learn the subthreshold principle: understand the physics of mosfets in weak inversion and how to utilize the exponential 𝐼−𝑉 relationship for low-power nonlinear dynamics.
2. Implement neuron models: design and simulate biologically plausible neuron models like the Izhikevich model. This includes understanding the neural dynamics.
3. Conduct power & timing analysis: * estimate energy per spike and static power consumption across different models.
4. Evaluate robustness: investigate the impact of process variations (e.g., mismatch) on neuron firing patterns and develop mitigation strategies in the software training loop.
Neural networks have become significant computation models in many areas of research and industry (e.g., computer
vision, speech recognition, etc.). As a result, there is a need for energy-efficient accelerators for edge applications like IoT,
requiring optimized hardware designs. One of the critical components of an ANN accelerator is the data interface. The
system bus is an internal communication path that allows information to be transferred between the main components
of the system. In our case, the system bus needs to link between the controller, ANN and other sub modules. It needs to
contain data, address and control buses and to have high-speed parallel communication, ensuring optimal throughput
and low latency. Also, this system bus must deal with challenges like priorities between modules, masking, and
interruptions.
The main goal of this project is to develop a system bus for an ANN Accelerator, enabling data exchange between
control unit, the ANN core and other sub modules.
Specific objectives:
Neural networks have become significant and are used in many areas of research and industry. Today’s computer
architecture has a major bottleneck in the transfer of data between memory and computation units, which makes it
difficult to perform the necessary computations. One of the solutions that has been proposed is Compute-in-memory
(CIM) architectures, to accelerate the computations. This project aims to design a controller for an ANN accelerator
system and its peripherals.
The main goal of this project is to develop a controller for an ANN accelerator, that can process input data, adapt it to
the network structure, and provide all necessary data and signals for the ANN.
Specific objectives:
Emerging memristors are novel circuit elements, originally described as the “fourth missing circuit element” and considered today as the future of nonvolatile memory. Different memristors have been developed and simulatively characterized by the Technion’s ASIC² research group, headed by Prof. Shahar Kvatinsky.
Some of the memristor devices have been manufactured by semiconductor companies (such as Tower Semiconductor, Winbond, and Weebit) and some of them were fabricated in academia by our collaborators from universities such as Stanford, Aachen, and Arizona State.
Our target is to experimentally measure and characterize memristors and to demonstrate their functionality for novel circuits in applications such as artificial intelligence, memory, and logic.
Compute-In-Memory (CiM) accelerates Deep Neural Networks (DNNs) by reducing energy-intensive weight
movement and enabling low-energy, high-density computation within memory arrays. While research spans
the CiM stack, most works focus on a single level (device, circuit, architecture, workload, or mapping) or design
point (e.g., one chip). A full-stack modeling tool is needed to evaluate system-level impacts and enable rapid
early-stage co-design.
MIT researchers developed CiMLoop, an open-source tool for modeling diverse CiM systems and exploring
cross-stack decisions. CiMLoop provides:
(1) a flexible specification for mapping workloads to circuits and architectures,
(2) an accurate energy model capturing interactions among DNN data, hardware representations, and
circuit behavior, and
(3) a fast statistical model for rapid design-space exploration.
CiMLoop enables researchers to evaluate, co-design, compare, and explore CiM designs efficiently across all
levels of the stack, fairly compare different implementations and rapidly explore the design space.
Project Goals:
In this project, the students will get acquainted with the CiMLoop tool, understand its usage and benefits, and
will use it to implement several research designs at varying levels of complexity.
The students will:
● Gain practical experience by installing and working with the CiM tool
● Implement couple of design examples to evaluate its usefulness
● Implement and evaluate an ongoing research design (e.g., GNN/Transformers) using CimLoop.
Compute-in-memory (CIM) systems can effectively reduce data movement overhead and improve energy efficiency compared to traditional von Neumann architectures. A key bottleneck in CIM systems, however, lies in the analog-to-digital conversion (ADC) stage. Generated by memristor array, currents are converted by ADC into digital values for subsequent processing. The performance, energy efficiency, and accuracy of this ADC strongly affect the overall CIM system.
For convolutional neural network (CNN) models, the first and last layers are typically more sensitive to quantization, while intermediate layers are relatively robust. Therefore, selecting an appropriate ADC resolution for different layers in is important to balance system throughput, accuracy, and energy efficiency.
In this project, students will design and simulate the functional behavior of an ADC described in the reference paper using Python or cadence Virtuoso. This project aims to develop fundamental skills in the CIM/ADC working principles, simulation, and modeling of emerging memory-based computing systems.
The goal of this project is to develop a simulation framework that reproduces the functional behavior of a memristor-based ADC (Q-cell) within a CIM system.
The students will:
● Understand the role of ADCs in compute-in-memory architecture, including the basic workflow of ACIM systems such as programming and inference.
● Implement a Y-Flash-based Q-cell (replacing the original PCM device), build two ADC architectures with 3-bit and 6-bit resolutions using Python or Cadence Virtuoso schematic design.
● Simulated responses to the input voltage, including voltages at nodes A and B, and the output of the Q-cell.
● Calculate and analyze key ADC parameters, including energy per operation, sampling
frequency, linearity metrics (DNL/INL) and ENOB.
Processing-In-Memory (PIM) is an emerging paradigm that addresses the von Neumann bottleneck by performing computation directly within memory arrays, thereby significantly reducing data movement and improving energy efficiency. Recent work has demonstrated flexible controllers (CtrlPIM [1]) capable of issuing microcoded instructions to such memory arrays. However, the memory array itself (MemArray) – which performs the actual in-memory computation – was not integrated in that work.
This proposed project focuses on implementing the memory component of a PIM system on FPGA, complementing the existing controller design.
System Overview
The target system is based on the previously proposed architecture, integrating:
-CPU
-Microcode-based PIM controller (CtrlPIM)
-Memory Array (MemArray)
The controller generates sequences of PIM commands, which are executed inside the memory array. This project completes the system by providing a hardware implementation of the MemArray, enabling end-to-end PIM execution on FPGA, see Figure 1.
Project Goals
The main objective of this project is to design and implement the MemArray block on FPGA, including its storage and compute capabilities. In this project, the students will:
•Understand the architecture of PIM systems and the role of the memory array
•Analyze the interface between the controller and the MemArray
•Design a hardware module that:
•Stores data in a structured array (rows/columns)
•Receives PIM commands from the controller
•Executes in-memory operations (e.g., vector operations, reductions, logic ops)
•Implement the design in Verilog/VHDL on FPGA
•Integrate the MemArray with an existing controller (or a driver environment)
•Validate correctness using test programs (e.g., reduction, compaction)
•Evaluate performance (latency, throughput, resource usage)
Recently, several nonvolatile memory (NVM) technologies, such as NAND Flash, PCM, ReRAM, and STT-MRAM, have emerged as promising candidates for digital and analog in-memory computation. Tower’s Y-Flash NVM, fully compatible with standard CMOS process, can be used as a building block which can be used in many artificial neural networks (ANNs) applications owing its multilevel characteristic.
In this project, you will develop an experimental setup to write the weights of an ANN to a Y-Flash memory array. You will learn the FPGA environment and use it to develop an experimental setup for digital control signals.
This project is part of the NEMO research project, where we aim to implement ultra-low-power ANN hardware accelerators.
Project Goals:
The goal of this project is to build a framework system that generates the digital control signals for using an FPGA platform.
The students will:
● Learn about emerging memory technologies and processing in memory for ANN hardware accelerators.
● Gain practical experience with FPGA platform combined with research purposes for experimental characterization.
