Computing-in-memory (CiM) has been a potential solution to break the memory wall and energy wall brought by the conventional computer architecture that separates the computing units and memory units. RRAM-based stateful logic is a kind of CiM that could implement any function in RRAM crossbar array. There are some efficient synthesis and mapping methods for 2D RRAM crossbar array. 3D RRAM crossbar array is denser and can support stateful logic in adjacent layers. The added dimension has created the flexibility to place the stateful logic in 3 dimensions instead of only 2 dimensions. However, there is few synthesis and mapping methods that could efficiently take advantage of the 3-dimension flexibility.
In this project, we develop a new synthesis and mapping method the RRAM-based stateful logic by taking use of the architecture of 3D RRAM crossbar array. The proposed method would be compared with the method of naively extending the conventional synthesis and mapping method for 2D crossbar to 3D in terms of cell usage, latency, and endurance.
For more information please contact Minhui Zou: minhui@campus.technion.ac.il
A memristive crossbar array consist of a grid of n×n memristors, each storing a single bit. Stateful logic techniques (e.g., MAGIC) support row/column bit-wise operations in O(1) time complexity. For example, storing the bitwise NOR of two columns of binary data in a third column, in one clock cycle. Essentially, vectored operations across rows and columns are performed in constant time. Creative techniques are required to efficiently utilize this capability.
Recent works demonstrate massive improvement to a variety of algorithms, when stateful logic is utilized efficiently. For example, general-purpose matrix multiplication is performed in O(n^2) time complexity rather than O(n^2.807) with traditional solutions (Strassen’s algorithm).
In this project, you choose a theoretical problem that you would like to explore, and demonstrate an efficient solution based on stateful logic. Hopefully you will invent various creative algorithmic techniques, and present massive improvements over traditional solutions.
In this project, we reveal the vulnerability of memristor computing systems by developing novel side-channel attacks to reverse engineer the NN structures of the NN models. To mitigate the vulnerability, we also propose efficient countermeasures. Both the attacks and countermeasures will be experimented on simulation models or physical platforms.
For more information please contact Minhui Zou: minhui@campus.technion.ac.il
Emerging memristors are novel circuit elements, originally described as the “fourth missing circuit element” and considered today as the future of nonvolatile memory. Different memristors have been developed and simulatively characterized by the Technion’s ASIC² research group, headed by Prof. Shahar Kvatinsky.
Some of the memristor devices have been manufactured by semiconductor companies (such as Tower Semiconductor, Winbond, and Weebit) and some of them were fabricated in academia by our collaborators from universities such as Stanford, Aachen, and Arizona State.
Our target is to experimentally measure and characterize memristors and to demonstrate their functionality for novel circuits in applications such as artificial intelligence, memory, and logic.
In this project, a Verilog controller will be implemented, synthesized and evaluated, along with small ASIC memory peripherals.
