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Ameer Haj Ali
Graduate Student

Research Experience

My research aims to enhance the performance of conventional computer systems, where I believe a key problem is the frequent data movement between the computing and memory units. To address that, I am moving the computation into the memory unit using emerging memory technologies, such as RRAM. I am investigating the benefits and drawbacks of these technologies to find the applications that can leverage them, with the goal of building a new processing-in-memory accelerator that maximizes the parallelism and energy efficiency in these applications.

I currently implemented efficient novel in-memory algorithms for fixed-point multiplication, vector dot product, Hadamard product and image convolution. Furthermore, I am working on redesigning the memory to guarantee maximum parallelism, which includes handling data transfer, partitioning of large matrices and data mapping. I also address and propose solutions for all the issues of computing in RRAM (e.g., peak power, IR drop, limitation of parallelism, endurance, etc.)

I finished four years of undergraduate studies in computer engineering at the Technion – Israel Institute of Technology in only three years, graduating summa cum laude and receiving the valedictorian honor*. During my undergraduate studies, I worked at Mellanox Technologies as a chip designer. I focused on creating design and automation tools that facilitated the formal and dynamic verification process.

As much as I love research I also love teaching. I started teaching at the Technion from my second semester of undergraduate studies. At the beginning I taught all levels of calculus and physics. Now, I am the TA in charge of Circuit Theory (044105, 400+ students) and Electronic Switching Circuits (044147, 250+ students).


* My valedictory speech on behalf of all undergraduate students at my B.Sc. commencement ceremony, with subtitles:


Conference Publications:

(1) Ameer Haj Ali, Rotem Ben-Hur, Nimrod Wald, and Shahar Kvatinsky, “Efficient Algorithms for In-memory Fixed Point Multiplication Using MAGIC,” Proceeding of the IEEE International Conference on Circuits and Systems (ISCAS 2018), submitted paper, May 2018.

(2) N. Talati, A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, P. E. Gaillardon, and S. Kvatinsky, “Practical Challenges in Delivering the Promises of Real Processing-in-Memory Machines,” Design, Automation, and Test in Europe DATE 2018.

(3) J. Ruben, R. Ben Hur, N. Wald, N. Talati, A. Haj Ali, P.E. Gaillardon, and S. Kvatinsky. “Memristive Logic: A Framework for Evaluation and Comparison,” International Symposium on Power and Timing Modeling, Optimization, and Simulations PATMOS 2017.

Journal Publications:

  • Ameer Haj Ali, Rotem Ben-Hur, Nimrod Wald, and Shahar Kvatinsky, “IMAGING – In-Memory AlGorithms for Image processiNG,” IEEE Transactions on Circuits and Systems I(TCAS I), 2017 (in preparation).
  • Tzofnat Greenberg, Ameer Haj Ali, and Shahar Kvatinsky, “Supporting the Momentum Algorithm Using a Memristor-Based Synapse,” IEEE TRANSACTIONS ON VERY LARGE-SCALE INTEGRATION (VLSI) SYSTEMS (TVLSI), 2017 (submitted paper).

Book Chapters:

(1) N. Talati, R. Ben Hur, N. Wald, A. Haj Ali, J. Reuben, and S. Kvatinsky, “mMPU – a Real Processing–in–Memory Architecture to Combat the von Neumann Bottleneck,” in Advanced Applications of Emerging NVM Devices, Springer Series in Advanced Microelectronics, 2017 (in press).
(2) J. Reuben, N. Talati, N. Wald, R. Ben Hur, A. Haj Ali, P.E. Gaillardon, and S. Kvatinsky, “A Taxonomy and Evaluation Framework for Memristive Logic,” in Handbook of Memristor Networks, Springer, 2017 (in press).


  • Ameer Haj Ali and Shahar Kvatinsky, “Beyond von-Neumann Computing,” Technion Research Day, November 2017.
  • Ameer Haj Ali, Rotem Ben-Hur, Nimrod Wald, and Shahar Kvatinsky, “In-memory Image Processing Algorithms,” Beyond CMOS: From Devices to Systems, June 2017.
  • Ameer Haj Ali, Nimrod Wald, and Shahar Kvatinsky, “Configurable Simulator for Multithreaded Processors,” Intel Collaborative Research Institute, May 2017.

Undergraduate research projects

  • “GPU Algorithms Development for In-Memory Processing.” Developed optimized algorithms to map the execution of highly parallel applications to the memory arrays enabling processing in memory which drastically improved the performance.
  • “In Memory Matrix Multiplication Simulator.” Implemented system and circuit level simulators for in memory matrix multiplication to evaluate different metrics and trade-offs.
  • “Configurable, Multi-threaded, Cycle Accurate, Processor Simulator.” Collaborated with researchers from CEVA, Inc. to build a generic simulator, which measures cycle-accurate performance for any application running on a wide variety of digital signal processors with different pipeline lengths, critical stages, cache hierarchy, number of execution/load/store/branch prediction units, multithreading methods, instruction set architecture, etc.

For these projects, the Technion twice awarded me “The System Architecture Labs Cluster” Prize for outstanding undergraduate projects.

Professional peer review activity

As part of my responsibility as a researcher, I am currently (or have been) involved in the peer review process of:

  • HPCA-2018
  • DATE-2018
  • ISCAS-2017
  • Microelectronics Journal
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