ABSTRACTPIM: BRIDGING THE GAP BETWEEN PIM TECHNOLOGY AND ISA
abstractPIM is a new compilation concept and flow which enables executing any function within the memory, using different stateful logic families and different instruction set architectures (ISAs). By separating the code generation into two independent components, intermediate representation of the code using target-independent ISA, and then microcode generation for a specific target machine, we provide a flexible flow with backward compatibility and lay foundations for a PIM compiler.
Using abstractPIM, we explore various logic technologies and ISAs and how they impact each other and discuss the challenges associated with it, such as the increase in execution time.
SUPERCONDUCTIVE LOGIC CIRCUITS WITH HALF FLUX QUANTUM PULSES
Superconductive technology is gaining significant interest for large scale, stationary data centers. The power-delay product of superconductive logic families exceeds complementary metal oxide semiconductor (CMOS) by more than five orders of magnitude, making superconductive technology one of the most energy efficient, high speed technologies available today. Automated design tools and technology scalability are essential to achieve high complexity, superconductive VLSI systems.
Superconductive circuits, however, suffer from low density integration as compared to CMOS, primarily due to the limited scalability of the inductors. To improve the scalability of superconductive logic, a logic family based on a novel JJ technology,2-Josephson junction (2\phi-JJ), has been proposed that eliminates the inductors.
In this project, three circuits which are functionally complete are presented which exploit this scalable inductor-less technology. This novel 2\phi-JJ technology represents the data as half flux quantum (HFQ) pulses, which improves the energy efficiency and speed as compared to standard superconductive logic such as rapid single flux quantum (RSFQ). Unlike RSFQ, the proposed circuits dynamically switch upon receiving an HFQ pulse, saving energy.
Moreover, a design methodology for this logic family is presented in this project. This methodology maintains the same DC operating point as RSFQ logic and considers the novel device. This logic family consists of only standard JJs and 2\phi-JJs, eliminating the inductors, producing more scalable, faster, and energy efficient circuits. A general methodology to convert a standard RSFQ cell library into a 2\phi-JJ logic cell library is described. The 2\phi-JJ logic cells produced by this conversion methodology are, on average, 2X faster and 3.2X more energy efficient than conventional RSFQ cells with similar parameter margins and yield characteristics.