Resources Undergraduate Projects

Hardware SecurityRF, Mixed Signal and Analog CircuitsComputer ArchitectureLogic with MemristorsOther

Hardware Security

Design and Security Analysis of an AES Encryption Module
Abstract:

Side Channel Analysis is a group of attacks that utilize side effects of implementations of cryptographic hardware to gain access to secrets. One of such attacks is a Differential Power Analysis (DPA). DPA is an extremely powerful technique that uses power consumption as a source of leakage. For this, many power traces of execution of cryptographic algorithm are collected and processed. Machine learning techniques are then used to correlate between the power traces and the secret keys. It was first published in 1996, and since then hundreds of works have been published on successful DPA attacks of different types and on protection methods.

Description:
High Precision Differential Sense Amplifier for Resistive Memories
Abstract:

Background: Resistive memory is a new technology based on a passive circuit element called Memristor, which changes its resistance value based on the current flowing through it. Memristors are nanoscale elements that can be easily integrated in a typical VLSI manufacturing process. Therefore, memristors can be combined with existing structures to create new circuits. Memristors have a list of unique properties, such as non-volatility, non-linearity and sensitivity to process that make them particularly attractive for security applications. One such application is a memristive hardware secure hash function, based on a memristor crossbar structure. This application uses differential read and requires high accuracy in the read path. In this project, the students will design a high precision differential sense amplifier required for an accurate read from the array based on the state-of-the-art technology.
Project Description:
At the first stage, the students will study the literature related to high precision differential current sense amplifiers. Then, they will choose a specific architecture and design the circuit. In the following stage, the students will simulate the circuit both as a stand-alone and when connected to a memristor crossbar array. The simulations will include noise and parameter variations. The main tool for design and simulation is Cadence Virtuoso.

In this project the students will acquire experience in advanced analog design and in using the Cadence Analog Design Environment.

Description:
Supervisor(s):

RF, Mixed Signal and Analog Circuits

Memristor-Based Phase Shifters
Abstract:

The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things (IoT) and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the real challenge is scaling multi-frequency/multiprotocol RF systems and memristors can help us achieve that!

Description:
Supervisor(s):
Requirements:
Waves & Distributed systems, Circuit Theory, RFIC course (recommended)

Computer Architecture

MRAM versus SRAM for non volatile FIFO
Abstract:

Toggle MRAM uses a 1 transistor, 1 MTJ cell to provide a simple, high-density memory. Everspin uses a patented Toggle cell design that delivers high reliability. Data are always non-volatile for 20-years at temperature. During a read, the pass transistor is activated and data is read by comparing the resistance of the cell to a reference device. During writes, the magnetic field from Write Line 1 and Write Line 2 writes the cell at the intersection of the two lines but does not disturb other cells on either line. MRAM products employ one transistor, one magnetic tunnel junction (MTJ) memory cell for the storage element. The MTJ is composed of a fixed magnetic layer, a thin dielectric tunnel barrier and a free magnetic layer. When a bias is applied to the MTJ, electrons that are spin-polarized by the magnetic layers traverse the dielectric barrier through a process known as tunneling.

Project Description:
– Study the theory of Magnetic RAM and its interface
– Write an interface on FPGA to standard SRAM 35nsec
– Make a circuit including a MRAM and a SRAM
– Connect the circuit to the FPGA and debug the interface with SRAM
– Compare SRAM and MRAM performances
– Write a FIFO interface for the MRAM and demonstrate functionality
– Propose a MRAM application and develop it on the FPGA Board

Description:
Supervisor(s):
New Non volatile Memory Technologies: FRAM Versus ReRAM
Abstract:

Nonvolatile memories that have traditionally been ROM (read only memory) until the advent of floating-gate technology. Floating-gate technology produced electrically erasable memories such as flash and EEPROM. These products allow for in-system programming but read and write access times are dissimilar. In fact, the write access times can be several orders of magnitude greater than the read access times. Ferroelectric random access memory or F-RAM is a true nonvolatile RAM because it combines the advantages of both RAM and nonvolatile memory. The write advantages over flash/EEPROM and non-volatility make it quite suitable for storing data in the absence of power.
Resistive random access memory. A form of non-volatile memory in which a pulse voltage is applied to a metal oxide thin film, creating massive changes in resistance to record ones and zeros. With a simple structure of metal oxide placed between electrodes, the manufacturing process is very simple, while still offering such excellent features as low power consumption and fast write.

Project Description: Study the theory of Ferroelectric RAM and Resistive RAM, Study the SPI and I²C interfaces, using available Libraries write an interface on FPGA to standard Serial RAM, design and make a circuit including a FRAM and a RRAM, connect the circuit to the FPGA and debug the interface, compare FRAM and RRAM performances by means of throughput and Magnetic Field Immunity, propose a FRAM and RRAM applications and demonstrate feasibility.

Description:
Supervisor(s):

Logic with Memristors

Executing state machines within a memristor-based memory
Abstract:

Nowadays, the performance of computer systems is significantly limited by the speed of the memory. Data transportation between the memory
and the processor is time-consuming and wasteful in energy.

One of the leading ideas for solving these issues is to transfer part of the processing capabilities of the processor into the memory itself. For data-
intensive applications, this means a significant increase in computing processing power, while saving a significant amount of time and energy.

A new computer architecture approach, based on a memristor-based memory, enables performing computations within the memory.
The memristor is a passive circuit element, predicted in 1971 by the circuit theorist Leon Chua. The first prototype of this element was unveiled
in 2008 by HP labs. The device remembers its history, by varying its own resistance, so it can be used for memory applications. It also enables
the formation of basic logic circuits, based on the MAGIC logic gate. The combine of memory with logic enables to perform logic operations
within the memory itself, thus to explore advanced non-von Neumann architectures.
Project description:
In this project, the students will design and implement an algorithm for executing state machines within a memristor-based memory. Such a
novel method enables to implement a processor within the memory, thus eliminate the need for an external processor in small systems, and
therefore reduces the limitations of today’s computer systems.

Description:
Supervisor(s):
In-Memory Searching Vs. Conventional Architectures
Abstract:

Background: Nowadays, the performance of computer systems is significantly limited by the speed of the memory. Data transportation between the memory and the processor is time consuming and wasteful in energy.
Searching quickly is one of the most desired capability in the big data era. In conventional architectures, as the data size increase, the latency for searching increases, since more data has to be transferred from the memory which stores the data to the processor which performs the searching. One of the leading ideas for solving these issue is to transfer the search process into the memory itself.
A new computer architecture approach, based on a memristor-based memory, enables performing computations within the memory.
The memristor is a passive circuit element, predicted in 1971 by the circuit theorist Leon Chua. The first prototype of this element was unveiled in 2008 by HP labs. The device remembers its history,by varying its own resistance, so it can be used for memory applications. It also enables the formation of basic logic circuits, based on the MAGIC logic gate. The combine of memory with logic enables to perform logic operations within the memory itself, thus to explore advanced non-von Neumann architectures.
In previous work we developed an algorithm for searching within memory.

Project Description:
In this project, the students will explore state of the art architectures which perform searching within big chunks of data and compare with results of in-memory computations.

Description:
Supervisor(s):
RRAM Basic Element Characterization and MAGIC implementation
Abstract:

Resistive Random Access Memory (RRAM) is an emerging technology based on the Memristor. It has made significant progress in the past decade as a competitive candidate for the next generation of non-volatile memory (NVM). But not only. Beyond the NVM applications, RRAM may also be used in Memristive Memory Computing applications. In this case RAM cells should go through a characterization procedure.

Project Description:
The project consists of learning Memristor technology and the process of characterization.
Study Memristor Basic Theory and specific Device Under Test (DUT)
Practice and control SMU & PS measurement techniques using LAN.
Design and implementation of a Test for DUT characterization
Learn MAGIC theory for in-memory computing
Implement a MAGIC gate in DC and for low frequency.
Design a test plan for MAGIC gate reliability test and evaluation of Mean Time Between Failures (MTBF).

Description:
Supervisor(s):
Efficient column reuse in a memristive memory processing unit
Abstract:

Background: Nowadays, the performance of computer systems is significantly limited by the speed of the memory. Data transportation between the memory and the processor is time consuming and wasteful in energy.

One of the leading ideas for solving these issues is to transfer part of the processing capabilities of the processor into the memory itself. For data-intensive applications, this means a significant increase in computing processing power, while saving a significant amount of time and energy.

For achieving that, we developed a new computer architecture approach where a memristive Memory Processing Unit (mMPU) replaces the memory. This novel memory with processing capabilities is based on memristors. The memristor is a passive circuit element, predicted in 1971 by the circuit theorist Leon Chua. The first prototype of this element was unveiled in 2008 by HP labs. The device remembers its history, by varying its own resistance, so it can be used for memory applications. It also enables the formation of basic logic circuits, based on the MAGIC logic gate. The combine of memory with logic enables to perform logic operations within the memory itself, thus to explore advanced non-von Neumann architectures.

In previous work, we developed a tool which outputs the execution sequence of any desired logic operation. This tool assumes the structure of the logic circuit is a tree, whereas it is truly a DAG (Directed Acyclic Graph). Improving the tool to consider that will probably improve the latency of the execution sequence the tool produces.

In this project, the students will improve the current Matlab code to consider the DAG-based circuit implications, by implementing the idea presented in [1].

Description:
Supervisor(s):

Other

A compliance current circuit w nanosec response time for ReRam Characterization
Abstract:

Background: ReRAM is an emerging technology in both Industrial and academic communities. Compliance current (CC) is a factor that can significantly influence ReRAM potential performance. State of art apparatus propose response time for CC circuit between 100usec and msec. This slow response limit accuracy potential of performing operation.

Project Description:

• Read Paper

• CC design

• SPICE Simulation

• Circuit implementation

• Performance comparison

Description:
Supervisor(s):
Requirements:
Computer organization and Design. Recommended: Lab1
Differential Power Analysis (DPA) of emerging technology memories
Abstract:

Background: DPA is an extremely powerful technique that uses power consumption as a source of leakage. For this, many power traces of execution of cryptographic algorithm are collected and processed. Machine learning techniques are then used to correlate between the power traces and the secret keys. ReRAM, FeRAM, and CBRAM are emerging memory technologies.

Project Description:

• Read Papers about DPA and AES (Advanced Encryption Standard)

• Implement SPI I/F on FPGA board

• Design AES Module

• Setup DPA attack

• Collect and Process Traces

Description:
Supervisor(s):
Requirements:
Computer organization and Design. Recommended: Lab1
STT-MRAM based Multistate Register using 22FDX GF libraries
Abstract:

Background: An STT-MRAM based multistate register will be designed, capable of storing multiple data bits within a single active register. The register compensates for the stochastic nature of STT-MRAM while enabling switching latencies compatible with modern microprocessor pipelines. To do so we shall use 22FDX Global Foundries libraries.

Project Description:

• Read Paper

• Hands-on VLSI tools & Library integration

• Design Register

• Demonstrate

Description:
Supervisor(s):
Requirements:
Perquisites: Computer organization and Design Recommended: Lab1
Spin-torque Transfer MRAM controller for Risc -V
Abstract:

Background: Writes to a memory array by manipulating electron spin with a polarizing current, performs like DRAM but requires no refresh, a significant reduction in switching energy compared to FS Toggle MRAM, highly scalable, enabling higher density memory products (sampling 1Gb in 2019), can interface with JEDEC DDR3 with minor modification, and is quite an attractive emerging memory. Let’s use it!

Project Description:

• Design a Memory I/F according to Standard JESD79-3F, with exceptions and improvements as required to SST-MRAM state of art.

• Implement on FPGA

• Connect it to RISC-V core

• Test it and compare to DRAM DDR3

Description:
Supervisor(s):
Requirements:
Computer organization and Design. Recommended: Lab1
Resources:
Undergraduate ProjectsOther