Artificial neural networks based on memristive devices are receiving increasing interest in recent years. These neural networks are using mature structures which are well mathematically defined but less biologically plausible. One of the more biologically plausible neural networks is the cellular nonlinear network. It is composed of localized connections between adjacent neurons. The system can automatically evolve to minimization points in the energy landscape of the system. How to use memristive devices (RRAM, PCM, etc) in this kind of neural network is not well studied. In this project, theories of the cellular nonlinear network will be studied and the possibilities of using memristive devices in these networks will be investigated. A simulation of a prototype cellular nonlinear neural network accounting for the behaviors of memristive devices as the synaptic connections should be carried out.
Study the working mechanism of the cellular neural network, carry out simulations to get hands-on about the network operation. Learn knowledge about memristive devices, for instance, resistive switching memory STT-MRAM (MTj) Construct a cellular neural network with memristive devices as connections. Simulate the memristive devices based cellular network with real memristive device behavior. Based on previous work, build the network using VLSI lab GK 22FDX MTj 22nm. Run simulations. Observe results. Prerequisites: Matlab/Python
SMEP: In order to emulate new and not yet available HW memory technologies, we propose to build a configurable FPGA plaorm. Since the project is a cooperaon with the GenPro (generic open source processor) consorum of the Innovaon Authority, the implementaon will use RISC-V devices of WDC consorum member.
Emerging memory technologies and their characteriscs RISC-V in general and SwerV-EH1 and Swerv-EL2 in details Get hands-on: Strax 10 Intel FPGA board: read-write to external DDR4 using both terminal and embedded ARM
*Previous implementaons of SweRV -EH1 and SweRV -EL2 on ASIC2 Lab servers
*Implement MEM Emulator using HW Verilog Pipeline. Proceed to simulaon and compare results to Expected theorecal performance by means of system clocks. Implement MEM Emulator using SweRV . Compare implementaons. RRAM case: Proceed to 32b MAGIC operaon. Analyze results, Propose ISA opmizaon. OPT: Demo during GenPro technology meeng.
RISC-V (pronounced “risk five”) is an open-source hardware instruction set architecture (ISA) based on established reduced instruction set computer (RISC) principles. The project began in 2010 at the University of California, Berkeley, but many contributors are volunteers not affiliated with the university. RISC V is a new architecture that is available under open, free, and non-restrictive licenses. It has widespread industry support from chip and device makers and is designed to be freely extensible and customizable to fit many applications. RISC V is a classic RISC architecture rebuilt for modern times. At its heart is an array of 32 registers containing the processor’s running state, the data is immediately operated on, and housekeeping information. RISC V comes in 32 bit and 64-bit variants, with register size changing to match. Western Digital SweRVCore EH 1 is a 32 bit, 2-way superscalar, 9 stage RISC V pipeline core. SweRVCore EH 2 was built off of the EH 1, but adds a dual threaded capability for additional SweRVCore EL 2 is a smaller core with moderate performance. It was designed to replace state machines and other logic functions in SoCs.
Project Requirements :
• Using ASIC 2 servers infrastructure learn and run both EL 2 and EH 1
• Using HSDSL lab FPGA implements both processors on FPGA, run Hello World
• Learn relevant Benchmarks, Check the enhanced performance of the double issue capability
• Demonstrate, report, and advise. Share the results on GitHub
This project is proposed in co operation with the ASIC 2 (Architectures, Systems, Intelligent Computing Integrated Circuits lab).
Hierarchical Connectivity Models (HCM) are used to describe hardware designs using high level programming language for implementations of VLSI algorithms and automation tools. With the growing complexity of digital hardware designs (VLSI), the need for automation tools is growing rapidly. In order to implement these tools, an efficient HCM tool which parses Hardware Description Language (HDL) files into an Object-Oriented Programming (OOP) environment is required.
This project purpose is to implement an Application Programming Interface (API) of HCM, which will be used in the “VLSI CAD” course. The implementation will be a C++ code, to be written in Visual Studio environment. The goal is to read Verilog files and represent their components and connectivity in a dedicated data structure.
Resistive Random-Access-Memory (ReRAM) is a very promising technology for Non-Volatile Memory (NVM), especially at the smaller process geometries. ReRAM is orders of magnitude faster and lower power consumption compared to Flash memories.
Weebit, incorporated in Israel in 2015, addresses the growing need for data storage and NVM technology with its new, ReRAM technology. Weebit’s ReRAM cell consists of 2 metal layers with a Silicon Oxide (SiOx) layer between them. In an initial, one-time, forming step, positive voltage is applied on the cell to form a conductive filament, and entering a Low Resistive State (LRS). After that – applying negative voltage can break the filament, moving to a High Resistive State (HRS), and positive and negative voltages can cause the cell to move from one state to the other.
In this project, Weebit’s 8×8 1T1R ReRAM array samples will be characterized and evaluated. ASIC² lab infrastructure will be used to test the switching capabilities of Weebit’s devices, including: switching time, HRS/LRS ratio, I-V curve, and endurance. Then, a Verilog-a device model will be fitted to the measured data. Finally, the fitted model will be used to simulate the devices in a large crossbar array.
– Learn about ReRAM and Weebit’s device features.
– Learn about ASIC² Python-based lab infrastructure.
– Using the lab infrastructure, characterize Weebit’s 1T1R device and array.
– Fit the characterized device to a Verilog-A model.
– Simulate the device in a large crossbar array using Virtuoso (Cadence).
Recently, several different memristive technologies (ReRAM, CBRAM, PCM, and STT-MRAM) have emerged as promising candidates for digital and analog in-memory computation. Since large-scale crossbars are still not available commercially, simulations are used to evaluate these computation methods. While simulations of a few devices are possible using simple SPICE tools, simulations of large-scale crossbars are very time-consuming without some sort of computation acceleration. Furthermore, a design tool to build and quickly analyze the results of such large-scale simulations are missing.
The Xyce Parallel Electronic Simulator is a SPICE-compatible circuit simulator, developed at Sandia National Laboratories. As a mature platform for large-scale parallel circuit simulation, Xyce supports standard capabilities available from commercial simulators, in addition to a variety of devices and models. Xyce is designed and written from the ground up to support large-scale parallel computing architectures. Xyce supports a canonical set of compact models. Verilog-A models may be processed into Xyce-compatible C++ code using the ADMS model compiler with the Xyce/ADMS back-end.
In this project, you will use the Xyce simulator to write and simulate accurate memristive models. Then, you will build a tool to control Xyce from Python, in order to simulate large crossbar arrays. Finally, you will use the tool to evaluate in-memory computation methods in large-scale memristive crossbars.
– Learn about memristors and the modeling of memristive devices.
– Learn about the Xyce simulator.
– Explore available memristor models available to use in Xyce.
– Develop a python tool to simulate memristive crossbars in Xyce.
– Learn about different in-memory computation methods using memristors.
– Use the tool to evaluate the performance, power and energy consumption of in-memory computation methods using memristive crossbars.
Smith-Waterman (SW) is a dynamic programming algorithm used for aligning two sequences against each other (considering Insertions, deletions, and mismatches). This alignment is needed for aligning a ‘read’ against the ‘reference genome’, which is a stage in the pipeline of DNA sequencing. DNA sequencing algorithms require a huge amount of data. Moving this data out of the memory and to the processing units requires a lot of time and power. Thus, to improve performance and power consumption we propose to implement these algorithms inside the memory in what is called a Processing-In-Memory (PIM) Architecture. In this project, SW is chosen to be implemented inside the memristor Memory Processing Unit (mMPU). It is a unit where data can be stored and processed in the same place.
• Study Smith-Waterman algorithm for Read Alignment
• Learn knowledge about memristors, memristors in crossbars, and mMPU (memristor memory processing unit)
• implement SW using memristors in the mMPU
• Simulate the memristive devices-based cellular network with real memristive device behavior.
Ferroelectric Field Effect Transistor (FeFET) memory has shown the potential to meet the requirements of the growing need for fast, dense, low power, and non-volatile memories. Integrating a layer of ferroelectric within the gate stack of a regular Field Effect Transistor (FET) enables the transistor to store data in the polarization state of the ferroelectric. 1T-FeFET memory arrays consider as promising technologies and are intensively explored. Since the FeFET is firstly a transistor, usage for logic implementation is explored too, mainly for accelerators implementations of different neural networks.
This project is a continue to project that showed the ability of implementation of OR, AND, XOR, XNOR, and CAM functions within a ferroelectric memory array. In this project, we look for appropriate application of binary neural network (BNN) which can benefit from the logic implementation within the memory. The target is to show an implementation of this application and compare it over state-of-the-art technologies. This project is part of the research and is suitable for undergraduate students who are thinking about a higher degree. The comparison will be handed using the Spice model of FeFET using Cadence Virtuoso to conduct the simulations.
The memristive Memory Processing Unit (mMPU) is a new process-in-memory computer architecture, which performs the computation without moving the data from the computer’s main memory (RAM). The logic implementation in the mMPU is based on emerging memory technology of ReRAM (resistive RAM), transpose memory array, and the MAGIC NOR operations, which reveal large vector operations.
The Bitlet model is a new analytical, parameterized, modeling tool, developed in the ASIC2 lab. The Bitlet model can be used to estimate the performance and the power of a PIM-based system and thereby assess the affinity of workloads for PIM as opposed to traditional computing.
In order to make Bitlet more beneficial, it has to be made more accessible to users by equipping it with new features and interactive graphical user interface. These additions will allow easy evaluation of various tradeoffs and clear visualization of relations among parameters.
In this project, we compare the different characteristics of two proposed 1T-FeFET arrays as the power, area, leakage, time parameters, endurance etc. This comparison will help us defining the applications which suitable for each array architecture and comparing over state-of-the-art technologies.
The comparison will be handed using Spice model of FeFET using Cadence Virtuoso to conduct the simulations.