Publications Journals

Publications:
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2020

N. Wainstein, G. Adam, E. Yalon, and Shahar Kvatinsky, "Radiofrequency Switches Based on Emerging Resistive Memory Technologies - A Survey", Proceedings of the IEEE (in press)
B. Hoffer, V. Rana, S. Menzel R. Waser, and S. Kvatinsky, "Experimental Demonstration of Memristor Aided Logic (MAGIC) Using Valence Change Memory (VCM)", IEEE Transactions on Electron Devices, June 2020. Paper for Experimental Demonstration of Memristor Aided Logic (MAGIC) Using Valence Change Memory (VCM)
D. Miron, D. Cohen Azarzar, B. Hoffer, M. Baskin, S. Kvatinsky, E. Yalon and L. Kornblum, "Oxide 2D Electron Gases as a Reservoir of Defects for Resistive Switching", Applied Physics Letters, Vol.116, Issue 22, June 2020 Paper for Oxide 2D Electron Gases as a Reservoir of Defects for Resistive Switching
H. Abo Hanna, L. Danial, S. Kvatinsky, and R. Daniel, "Cytomorphic Electronics with Memristors for Modeling Fundamental Genetic Circuits", IEEE Transactions on Biomedical Circuits and Systems, Vol. 14, pp. 386-401, June 2020. Paper for Cytomorphic Electronics with Memristors for Modeling Fundamental Genetic Circuits

2019

L. Danial, E. Pikhay, E. Herbelin, N. Wainstein, V. Gupta, N. Wald, Y. Roizin, R. Daniel, and S. Kvatinsky, "A Low-Power Memristive Operation Mode of Two-Terminal Floating-Gate Transistors for Analogue Neuromorphic Computing", Nature Electronics, Vol. 2, pp. 596-605, December 2019.
Jacobs Best Paper Award
Paper for A Low-Power Memristive Operation Mode of Two-Terminal Floating-Gate Transistors for Analogue Neuromorphic Computing
R. Ben-Hur, R. Ronen, A. Haj-Ali, D. Bhattacharjee, A. Eliahu, N. Peled, and S. Kvatinsky, "SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (In press) Paper for SIMPLER MAGIC: Synthesis and Mapping of In-Memory Logic Executed in a Single Row to Improve Throughput
B. Perach and S. Kvatinsky, "An Asynchronous and Low-Power True Random Number Generator using STT-MTJ", IEEE Transactions on Very Large Scale Integration Systems, Vol. 27, No. 11, pp. 2473-2484, November 2019. Paper for An Asynchronous and Low-Power True Random Number Generator using STT-MTJ
M. Ramadan, N. Wainstein, R. Ginosar, S. Kvatinsky, "Adaptive Programming in Multi-Level Cell ReRAM", Microelectronics Journal, Vol. 90, pp. 169-180, August 2019. Paper for Adaptive Programming in Multi-Level Cell ReRAM
N. Wald and S. Kvatinsky, "Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic", Microelectronics Journal, Vol. 86, pp. 22-33, April 2019 Paper for Understanding the influence of device, circuit and environmental variations on real processing in memristive memory using Memristor Aided Logic
T. Greenberg, R. Mazor, A. Haj-Ali, and S. Kvatinsky, "Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 66, No. 4, pp. 1571-1583, April 2019. Paper for Supporting the Momentum Training Algorithm Using a Memristor-Based Synapse
N. Talati, H. Ha, B. Perach, R. Ronen, and S. Kvatinsky, "CONCEPT: A Column Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM", IEEE Micro, Vol. 39, No. 1, pp. 33-43, January/February 2019. Paper for CONCEPT: A Column Oriented Memory Controller for Efficient Memory and PIM Operations in RRAM

2018

E. Giacomin, T. Greenberg, S. Kvatinsky, and P.-E. Gaillardon, "A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 62, No. 2, pp. 643-654, February 2019. Paper for A Robust Digital RRAM-based Convolutional Block for Low-Power Image Processing and Learning Applications
A. Haj-Ali, R. Ben-Hur, N. Wald, R. Ronen, and S. Kvatinsky, "IMAGING-In-Memory AlGorithms for Image processiNG", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No 12, pp. 4258-4271, December 2018. Paper for IMAGING-In-Memory AlGorithms for Image processiNG
L. Danial, N. Wainstein, S. Kraus, and S. Kvatinsky, "Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs using a Memristive Neuromorphic Architecture", IEEE Transactions on Emerging Topics in Computational Intelligence, Vol. 2, No.5, pp. 396-409, October 2018. Paper for Breaking Through the Speed-Power-Accuracy Tradeoff in ADCs using a Memristive Neuromorphic Architecture
N. Wainstein and S. Kvatinsky, "A Lumped RF Model for Nanoscale Memristive Devices and Non-Volatile Single-Pole Double-Throw Switches", IEEE Transactions on Nanotechnology, vol. 17, no. 5, pp. 873-883, September 2018. Paper for A Lumped RF Model for Nanoscale Memristive Devices and Non-Volatile Single-Pole Double-Throw Switches
A. Haj Ali, R. Ben Hur, N. Wald, R. Ronen, and S. Kvatinsky, "Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing", IEEE Micro, Vol. 38, No. 5, pp. 13-21, September/October 2018. Paper for Not in Name Alone: A Memristive Memory Processing Unit for Real In-Memory Processing
N. Wainstein and S. Kvatinsky, "TIME – Tunable Inductors using MEmristors", IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 65, No. 5, pp. 1505-1515, May 2018. Paper for TIME – Tunable Inductors using MEmristors
L. Danial, N. Wainstein, S. Kraus, and S. Kvatinsky, "DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors", IEEE Journal on Emerging and Selected Topics in Circuits and Systems, Vol. 8, No. 1, pp. 146-158, March 2018. Paper for DIDACTIC: A Data-Intelligent Digital-to-Analog Converter with a Trainable Integrated Circuit using Memristors
A. Doz, I. Goldstein, and S. Kvatinsky, "Analysis of the Row Grounding Method in a Memristor-Based Crossbar Array", International Journal of Circuit Theory and Applications, Vol. 46, No. 1, pp. 122-137, January 2018 Paper for Analysis of the Row Grounding Method in a Memristor-Based Crossbar Array

2017

A. Pedram, S. Richardson, S. Galal, S. Kvatinsky and M. Horowitz, "Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era", IEEE Design and Test, Vol. 34, No. 2, pp. 39-50, April 2017 Paper for Dark Memory and Accelerator-Rich System Optimization in the Dark Silicon Era

2016

Y. Cassuto, S. Kvatinsky, and E. Yaakobi, "Information-Theoretic Sneak Path Mitigation in Memristor Crossbar Arrays", IEEE Transaction on Information Theory, Vol. 62, No. 9, pp. 4801-4814, September 2016. Paper for Information-Theoretic Sneak Path Mitigation in Memristor Crossbar Arrays
N. Talati, S. Gupta, P. Mane, and S. Kvatinsky, "Logic Design within Memristive Memories Using Memristor Aided loGIC (MAGIC)", IEEE Transactions on Nanotechnology, Vol. 15, No. 4, pp. 635-650, July 2016 Paper for Logic Design within Memristive Memories Using Memristor Aided loGIC (MAGIC)
A. Morad, L. Yavits, S. Kvatinsky, and R. Ginosar, "Resistive GP-SIMD Processing In-Memory", ACM Transactions on Architecture and Code Optimization, Vol. 12, No. 4, Article 57, January 2016 Paper for Resistive GP-SIMD Processing In-Memory

2015

L. Yavits, S. Kvatinsky, A. Morad, and R. Ginosar, "Resistive Associative Processor", IEEE Computer Architecture Letters, Vol. 14, No. 2, July-December 2015
Best of CAL winner 2015
Paper for Resistive Associative Processor
D. Soudry, D. Di Castro, A. Gal, A. Kolodny, and S. Kvatinsky, "Memristor-based Multilayer Neural Networks with Online Gradient Descent Training", IEEE Transactions on Neural Networks and Learning Systems , Vol. 26, No. 10, pp. 2408-2421, October 2015 Paper for Memristor-based Multilayer Neural Networks with Online Gradient Descent TrainingSupplementary for Memristor-based Multilayer Neural Networks with Online Gradient Descent Training
R. Patel, S. Kvatinsky, E. G. Friedman, and A. Kolodny, "Multistate Register Based on Resistive RAM", IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 23, No. 9, pp. 1750-1759, September 2015 Paper for Multistate Register Based on Resistive RAM
S. Kvatinsky, M. Ramadan, E. G. Friedman, and A. Kolodny, "VTEAM – A General Model for Voltage Controlled Memristor", Transactions on Circuits and Systems II: Express Briefs, Vol. 62, No. 8, pp. 786-790, August 2015 Paper for VTEAM – A General Model for Voltage Controlled Memristor

2014

Y. Levy, J. Bruk, Y. Cassuto, E. G. Friedman, A. Kolodny, E. Yaacobi, and S. Kvatinsky, "Logic Operation in Memory Using a Memristive Akers Array", Microelectronics Journal, Vol. 45, No. 11, pp. 1429-1437, November 2014 Paper for Logic Operation in Memory Using a Memristive Akers Array
S. Kvatinsky, D. Belousov, S. Liman, G. Satat, N. Wald, E. G. Friedman, A. Kolodny, and U. C. Weiser, "MAGIC – Memristor Aided LoGIC", IEEE Transactions on Circuits and Systems II: Express Briefs, Vol. 61, No. 11, pp. 895- 899, November 2014. Paper for MAGIC – Memristor Aided LoGIC
S. Kvatinsky, N. Wald, G. Satat, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based Material Implication (IMPLY) Logic: Design Principles and Methodologies", IEEE Transactions on Very Large Scale Integration (VLSI), Vol. 22, No. 10, pp. 2054-2066, October 2014 Paper for Memristor-based Material Implication (IMPLY) Logic: Design Principles and Methodologies
S. Kvatinsky, Y. H. Nacson, Y. Etsion, E. G. Friedman, A. Kolodny, and U. C. Weiser, "Memristor-based Multithreading", IEEE Computer Architecture Letters, Vol. 13, No. 1, pp. 41-44, January-June 2014 Paper for Memristor-based Multithreading

2013

S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "The Desired Memristor for Circuit Designers", IEEE Circuits and Systems Magazine, second quarter, Vol. 13, No. 2, pp. 17-22, second quarter 2013 Paper for The Desired Memristor for Circuit Designers
S. Kvatinsky, E. G. Friedman, A. Kolodny, and U. C. Weiser, "TEAM - ThrEshold Adaptive Memristor Model", IEEE Transactions on Circuits and Systems I: Regular Paper, Vol. 60, No. 1, pp. 211-221, January 2013
2015 Guillemin-Cauer Best Paper Award
Paper for TEAM - ThrEshold Adaptive Memristor Model