News & Events

Today, we had the wonderful opportunity to present our research to the participants of the ACRC course on "AI Datacenter Hardware Architecture" taught by Gil Bloch from NVIDIA at the Technion-The Faculty of ECE (The Andrew & Erna Viterbi Faculty of Electrical & Computer Engineering).
May 21, 2024
Today, we had the wonderful opportunity to present our research to the participants of the ACRC course on "AI Datacenter Hardware Architecture" taught by Gil Bloch from NVIDIA at the Technion-The Faculty of ECE (The Andrew & Erna Viterbi Faculty of Electrical & Computer Engineering).
Arjun Tyagi presented his paper "Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays" at The 2024 International Symposium on Circuits and Systems (ISCAS), held in Singapore.
May 20, 2024
The paper introduces a 1S1R model tailored to a VO2-based selector and TiN/TiOx/HfOx/Pt RRAM device. We present simulations of 1R and 1S1R arrays, incorporating all parasitic parameters, across a range of array sizes from 4 × 4 to 512 × 512. We evaluate the performance of Memristor-Aided Logic (MAGIC) gates in terms of switching delay, power consumption, and readout margin, and provide a comparative evaluation with passive 1R arrays.
Arjun Tyagi presented his paper "Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays" at The 2024 International Symposium on Circuits and Systems (ISCAS), held in Singapore.
Today we participated at The Annual Graduate Student Research Day of Technion-The Faculty of ECE (The Andrew & Erna Viterbi Faculty of Electrical & Computer Engineering).
Apr 03, 2024
So what research topics we prepared for our presentations this time?
Today we participated at The Annual Graduate Student Research Day of Technion-The Faculty of ECE (The Andrew & Erna Viterbi Faculty of Electrical & Computer Engineering).
Jiang Li presented his paper "A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing" at The 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), held in Valencia, Spain.
Mar 25, 2024
The paper proposes a concealable RRAM PUF based on an RRAM crossbar array, utilizing the differential resistive switching characteristics of two RRAMs to generate keys. This RRAM PUF is compatible with in-memory computing (IMC), and they can be implemented using the same RRAM crossbar array.
Jiang Li presented his paper "A Concealable RRAM Physical Unclonable Function Compatible with In-Memory Computing" at The 2024 Design, Automation & Test in Europe Conference & Exhibition (DATE), held in Valencia, Spain.
Prof. Kvatinsky gave a talk at George Washington University, Washington DC, about "Real Processing-in-Memory using Memristive Memory Processing Unit."
Mar 12, 2024
Congratulations to Prof. Shahar Kvatinsky, who was promoted to Full Professor!
Mar 07, 2024
We are delighted to announce that Prof. Kvatinsky won the European Research Council (ERC) Proof-of-Concept grant!
Jan 21, 2024
Read the full article (Hebrew) here.
We are delighted to announce that Prof. Kvatinsky won the European Research Council (ERC) Proof-of-Concept grant!
Our paper entitled “Assessing the Performance of Stateful Logic in 1-Selector-1-RRAM Crossbar Arrays” was accepted to ISCAS 2024!
Jan 16, 2024
Congratulations to all the authors: Arjun Tyagi, Ronny Ronen and Shahar Kvatinsky.
Noa Aflalo presented her paper "Bitwise Logic using Phase Change Memory Devices Based on the Pinatubo Architecture" at the International Conference on VLSI Design 2024.
Jan 09, 2024
Our paper entitled "Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture" was accepted to VLSID 2024!
Dec 06, 2023
Congratulations to all the authors: Noa Aflalo, Eilam Yalon, and Shahar Kvatinsky.
Our paper entitled "A Concealable RRAM Physically Unclonable Function Compatible with In-Memory Computing" was accepted to DATE 2024!
Nov 12, 2023
Congratulations to all the authors: Jiang Li, Yijun Cui, Chenghua Wang, Weiqiang Liu and Shahar Kvatinsky.