News & Events

Kunal Korgaonkar has given a seminar in the EE department

June 27th, 2018

Kunal Korgaonkar, an intern at ASIC2 from Jacobs School of Engineering, UC San Diego, has given a seminar on “Where Bypass Triumphs Replacement: How emerging memory technologies will change the cache hierarchies” in the EE department on June 27.

Increasing the capacity of the Last Level Cache (LLC) can help scale the memory wall. Due to prohibitive area and leakage power, however, growing conventional SRAM LLC already incurs diminishing returns. Emerging Non-Volatile Memory (NVM) technologies like Spin-Torque Transfer RAM (STTRAM) promise high density and low leakage, thereby offering an attractive alternative for building large capacity LLCs. However, these technologies have significantly longer write latency compared to SRAM, which interferes with reads and severely limits their performance potential. Despite the recent work showing the write latency reduction at NVM technology level, practical considerations like high yield and low bit error rates will result in a significant loss of NVM density when these techniques are implemented. Therefore, improving the write latency while compromising on the density results in sub-optimal usage of the NVM technology. In this talk, I’ll present a novel STTRAM LLC design that mitigates the long write latency, thereby delivering SRAM like performance while preserving the benefits of high density. Detailed simulation of traditional SPEC CPU 2006 suite, as well as important industry workloads running on a 4-core system, shows that our proposal delivers on an average 26% performance improvement over a baseline LLC design using 8MB STTRAM while reducing the memory system energy by 10%. Our design outperforms a similar area SRAM LLC by nearly 18%, thereby making NVM technology an attractive alternative for future high-performance computing. This talk is based on joint work between UC San Diego and Intel labs and has appeared in ISCA 2018 [Density Tradeoffs of Non-Volatile Memory as a Replacement for SRAM based Last Level Cache – Kunal Korgaonkar et al.].