The growing demand to connect up the world is pushing wireless systems to be smaller than ever. This is part of the increasing move to a data driven world with billions of connected devices in the era of the Internet of Things and space and energy are critical design criteria. Traditionally, miniaturization was possible owing to a focus in a single frequency and a single communication protocol. However, the real challenge is scaling multi-frequency/multi-protocol RF systems. It is highly desirable to have adaptable RF-chains, which means adaptable filters, amplifiers, matching networks, etc.
Novel memristors have shown high performance at high-frequency i.e., low insertion loss, high isolation and high cutoff frequency. The non-volatility of memristors implies that no bias voltage or current is required to maintain a particular state, hence reducing the energy consumption. The small size of memristors could improve the density of transceiver chains in multiple-input multiple-output (MIMO) systems. Thus, these devices could stand as a leading contender in RF applications and as an alternative to MEMS and transistors. By decreasing the losses in the TX/RX chain, the amount, size and/or gain of amplifiers, phase shifters, filters, and others could be reduced, hence reducing power, area and costs.
Our work is focused on RF memristor modeling, memristive single-pole double-throw (SPDT) switches, and memristor-based tunable devices.
Neuromorphic Engineering has emerged as an exciting research area, primarily owing to the paradigm shift from conventional computing architectures to data-driven and cognitive computing beyond Von-Neumann. Encouraged by the ever-growing data-rich world, and inspired by the attractive features of neurobiology the neuromorphic engineering holds a promising future. With the imminent need for intelligent, reconfigurable, energy-efficient, fault-tolerant, adaptive and versatile computing. An interdisciplinary technology that combines biology, physics, mathematics, computer science, and electronic engineering to design artificial neural systems.
Hardware artificial neural networks are receiving a widespread attention as potential new architectures and models implementation for computing a wide variety of problems. Pattern classification, object/face recognition, image processing, signal processing, natural language processing, and machine learning algorithms, are few examples where conventional computers perform poorly compared to our brain. The massively parallel processing power of the neural network lies in the cooperation of highly interconnected computing elements (neurons) with non-volatile long-term memory (synapses). For the design of Artificial Neural Networks, emerging non-volatile memory technologies (namely, memristive technologies) are used since they are regarded as promising devices for modeling synapses in the realization of artificial neural systems for their nanoscale size, analog storage properties, low energy, and non-volatility.
Analog-to-digital converter (ADC) and digital-to-analog converter (DAC) are ubiquitous components that exist in every data-driven acquisition system and mixed-signal circuit. Data converters are the link between the digital domain of signal processing and the real world of analog transducers. This research is based on brain-inspired approaches to design smart ADC and DAC that could be reconfigured in real-time for general purpose applications.
The research uses emerging memory (memristors) integrated with conventional CMOS technology, and encouraged by artificial intelligent neural networks architecture, to break through the speed-power-accuracy tradeoff in modern data converters beyond Moore’s law.
Novel ADC/DAC configuration that is calibrated using an artificial-intelligence neural network technique are designed in ASIC2 labs and fabricated with TowerJazz labs collaboration. The proposed technique is demonstrated on an adaptive and self-calibrated ADC/DAC that can be configured on-chip in real time. These circuits use an online supervised machine learning algorithms. These algorithms fit multiple full-scale voltage ranges, and sampling frequencies by iterative synaptic adjustments, while inherently providing mismatch calibration and noise tolerance. The findings constitute a promising milestone towards scalable data-driven converters using deep neural networks.
Cytomorphic electronics is a novel field of designing noise tolerant ultra-low power cell-inspired circuits. The main goals oft his field are to simulate cells, organs, and tissues while considering the stochastic behavior of a single cell and cell-to cell variation, distortion, and cross-talk using mixed-signal integrated electronics. Such simulations are computationally intensive and can take weeks using modern digital hardware. Additionally, cytomorphic electronics is used to design novel large-scale synthetic biological systems by providing a fast and simple emulative framework. Furthermore, the field has aided in the design of electronic circuits and networks inspired by molecular biology, with uniquely emergent characteristics and concepts to be adopted for energy-efficient hardware realization.
A joint research with prof. Ramez Daniel from Biomedical Engineering faculty at the Technion is initiated to design, model and fabricate cytomorphic integrated circuits by emerging memory technologies and their biological counterparts.